Searched refs:REG (Results 151 - 175 of 296) sorted by relevance

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/linux-master/drivers/gpu/drm/amd/display/dc/gpio/
H A Dhw_ddc.c43 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_link_encoder.c42 #define REG(reg)\ macro
H A Ddcn201_hubp.c32 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_factory_dcn20.c59 #define REG(reg_name)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_factory_dcn30.c66 #define REG(reg_name)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_factory_dcn32.c59 #define REG(reg_name)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dio_link_encoder.c40 #define REG(reg)\ macro
H A Ddcn301_panel_cntl.c41 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_afmt.c35 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_aux.c36 #define REG(reg_name)\ macro
132 if (REG(AUX_RESET_MASK)) {
143 if (REG(AUX_RESET_MASK)) {
197 if (REG(AUXN_IMPCAL)) {
/linux-master/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hubp.c32 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_mpc.c29 #define REG(reg)\ macro
388 if (REG(MUX[opp_id]))
407 if (opp_id < MAX_OPP && REG(MUX[opp_id]))
488 if (opp_id < MAX_OPP && REG(MUX[opp_id]))
H A Ddcn10_hubbub.c35 #define REG(reg)\ macro
54 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A)) {
64 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B)) {
74 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C)) {
84 if (REG(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D)) {
625 if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {
/linux-master/drivers/net/ethernet/freescale/fs_enet/
H A Dmac-fcc.c71 #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
72 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
/linux-master/drivers/gpu/drm/amd/display/dc/hwss/dce120/
H A Ddce120_hwseq.c42 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/dcn35/
H A Ddcn35_hubp.c30 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c31 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn301/
H A Ddcn301_optc.c35 #define REG(reg)\ macro
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr_vbios_smu.c40 #define REG(reg_name) \ macro
/linux-master/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Ddcn301_smu.c39 #define REG(reg_name) \ macro
/linux-master/drivers/scsi/
H A Dsun_esp.c32 #define dma_read32(REG) \
33 sbus_readl(esp->dma_regs + (REG))
34 #define dma_write32(VAL, REG) \
35 sbus_writel((VAL), esp->dma_regs + (REG))
H A Dncr53c8xx.h899 #define REG(r) REGJ (nc_, r) macro
1089 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1092 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1095 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1161 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1164 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
/linux-master/drivers/gpu/drm/amd/display/dc/dpp/dcn10/
H A Ddcn10_dpp_dscl.c43 #define REG(reg)\ macro
549 if (REG(SCL_VERT_FILTER_INIT_BOT)) {
565 if (REG(SCL_VERT_FILTER_INIT_BOT_C)) {
672 if (REG(SCL_BLACK_OFFSET)) {
/linux-master/drivers/gpu/drm/panel/
H A Dpanel-novatek-nt39016.c70 #define RV(REG, VAL) { .reg = (REG), .def = (VAL), .delay_us = 2 }
/linux-master/drivers/gpu/drm/amd/display/dc/optc/dcn30/
H A Ddcn30_optc.c35 #define REG(reg)\ macro
251 if (REG(OPTC_MEMORY_CONFIG))

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