Searched refs:pixel_clock (Results 26 - 50 of 86) sorted by relevance

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/haiku/src/add-ons/accelerants/nvidia/
H A DSetDisplayMode.c44 LOG(1, ("SETMODE: requested target pixelclock %ukHz\n", target.timing.pixel_clock));
126 LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
130 LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
/haiku/headers/private/graphics/vesa/
H A Dvesa.h136 uint32 pixel_clock; // in Hz member in struct:crtc_info_block
/haiku/src/add-ons/accelerants/matrox/
H A DSetDisplayMode.c62 LOG(1, ("SETMODE: requested target pixelclock %dkHz\n", target.timing.pixel_clock));
105 LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
112 LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
349 status = mil2_dac_set_pix_pll((target.timing.pixel_clock)/1000.0, colour_depth1);
/haiku/src/add-ons/accelerants/skeleton/engine/
H A Ddac.c163 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;
166 req_pclk = (target.timing.pixel_clock)/1000.0;
227 float req_pclk = target.timing.pixel_clock/1000.0;
H A Dtvout.c1000 tv_target.timing.pixel_clock =
1010 tv_target.timing.pixel_clock = (calc_pclk * 1000);
1018 pix_period = (1000000000 / ((float)tv_target.timing.pixel_clock)) + 0.5;
/haiku/src/add-ons/accelerants/radeon_hd/
H A Dmode.cpp343 uint32 hfreq = mode->timing.pixel_clock / mode->timing.h_total;
351 uint32 vfreq = mode->timing.pixel_clock / ((mode->timing.v_total
363 mode->timing.pixel_clock, mode->timing.h_display,
414 int refresh = mode->timing.pixel_clock * 1000
H A Ddisplayport.cpp378 if (mode->timing.pixel_clock <= maxPixelClock)
410 if (mode->timing.pixel_clock <= maxPixelClock)
414 if (mode->timing.pixel_clock <= maxPixelClock)
421 if (mode->timing.pixel_clock <= maxPixelClock)
854 encoder_dig_setup(connectorIndex, mode->timing.pixel_clock,
874 encoder_dig_setup(connectorIndex, mode->timing.pixel_clock,
878 mode->timing.pixel_clock, 0, encoderConfig);
895 encoder_dig_setup(connectorIndex, mode->timing.pixel_clock,
899 mode->timing.pixel_clock, 0, encoderConfig);
/haiku/headers/private/graphics/common/
H A Dedid.h94 uint16 pixel_clock; // in 10 kHz member in struct:__anon89
/haiku/src/add-ons/accelerants/matrox/engine/
H A Dtvp3026.c50 target.timing.pixel_clock = (f_need * 1000);
122 target.timing.pixel_clock = (f_need * 1000);
H A Dmga_maven.c270 req_pclk = (target.timing.pixel_clock)/1000.0;
310 req_pclk = (target.timing.pixel_clock)/1000.0;
342 float req_pclk = target.timing.pixel_clock/1000.0;
575 float req_pclk = target.timing.pixel_clock/1000.0;
/haiku/src/add-ons/accelerants/skeleton/
H A DSetDisplayMode.c61 LOG(1, ("SETMODE: requested target pixelclock %dkHz\n", target.timing.pixel_clock));
140 LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
147 // LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
/haiku/src/add-ons/accelerants/neomagic/engine/
H A Dnm_dac.c142 req_pclk = (target.timing.pixel_clock)/1000.0;
210 float req_pclk = target.timing.pixel_clock/1000.0;
/haiku/src/add-ons/accelerants/via/
H A DSetDisplayMode.c61 LOG(1, ("SETMODE: requested target pixelclock %dkHz\n", target.timing.pixel_clock));
140 LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock));
147 // LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock));
/haiku/src/servers/app/
H A DScreen.cpp34 return rint(10 * float(mode.timing.pixel_clock * 1000)
166 mode.timing.pixel_clock = ((uint32)mode.timing.h_total
/haiku/src/add-ons/accelerants/via/engine/
H A Ddac.c172 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;
175 req_pclk = (target.timing.pixel_clock)/1000.0;
259 float req_pclk = target.timing.pixel_clock/1000.0;
406 float req_pclk = target.timing.pixel_clock/1000.0;
H A Dtvout.c1000 tv_target.timing.pixel_clock =
1010 tv_target.timing.pixel_clock = (calc_pclk * 1000);
1018 pix_period = (1000000000 / ((float)tv_target.timing.pixel_clock)) + 0.5;
/haiku/src/add-ons/accelerants/nvidia/engine/
H A Dnv_i2c.c583 LOG(4,("clock=%f MHz\n", timing->pixel_clock / 100.0));
698 if (edid_timing.pixel_clock <= 0/* || edid_timing.sync != 3*/)
706 specs->timing.pixel_clock = edid_timing.pixel_clock * 10;
762 LOG(4,("I2C: specsEDID: timing.pixel_clock %.3f Mhz\n", specs->timing.pixel_clock / 1000.0));
H A Dnv_dac.c205 target.timing.pixel_clock = si->ps.p1_timing.pixel_clock;
208 req_pclk = (target.timing.pixel_clock)/1000.0;
336 float req_pclk = target.timing.pixel_clock/1000.0;
/haiku/src/add-ons/accelerants/intel_extreme/
H A DPorts.cpp1052 fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
1254 hardwareTarget.pixel_clock * 1000 / (hardwareTarget.h_total * hardwareTarget.v_total));
1259 hardwareTarget.pixel_clock * 1000 / (hardwareTarget.h_total * hardwareTarget.v_total));
1344 fPipe->ConfigureClocks(divisors, hardwareTarget.pixel_clock,
1501 fPipe->ConfigureClocks(divisors, target->timing.pixel_clock, extraPLLFlags);
1865 uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
1883 ret_m = timing.pixel_clock * ret_n / linkspeed;
1955 uint32 bps = timing.pixel_clock * bitsPerPixel * 21 / 20;
1974 uint64 ret_m = timing.pixel_clock * ret_n * bitsPerPixel / linkspeed;
1992 ret_m = timing.pixel_clock * ret_
[all...]
/haiku/src/add-ons/accelerants/radeon/
H A Dpll.c285 tweaked_mode->timing.pixel_clock = crt_freq;
406 // mode->timing.pixel_clock must be in Hz because required accuracy in TV-Out mode
426 SHOW_FLOW( 2, "freq=%ld", mode->timing.pixel_clock );
428 Radeon_CalcPLLDividers( &pll, mode->timing.pixel_clock, 0, dividers );
433 // mode->timing.pixel_clock must be in Hz because required accuracy in TV-Out mode
H A DSetDisplayMode.c165 mode->timing.pixel_clock = fp_info->dot_clock;
182 mode->timing.pixel_clock *= 1000;
255 mode->timing.pixel_clock /= 1000;
271 //if( mode->timing.pixel_clock )
/haiku/src/add-ons/accelerants/common/
H A Ddecode_edid.c145 timing->pixel_clock = raw->pixel_clock;
242 } else if (raw->detailed_timing.pixel_clock > 0) {
/haiku/src/add-ons/accelerants/neomagic/
H A DSetDisplayMode.c63 LOG(1, ("SETMODE: requested target pixelclock %dkHz\n", target.timing.pixel_clock));
/haiku/src/add-ons/accelerants/3dfx/
H A D3dfx_mode.cpp209 bool clock2X = mode.timing.pixel_clock > si.maxPixelClock / 2;
308 uint32 pllFreq = TDFX_CalcPLL(mode.timing.pixel_clock);
/haiku/src/bin/screenmode/
H A Dscreenmode.cpp69 printf("%" B_PRIu32 " %u %u %u %u %u %u %u %u ", timing.pixel_clock / 1000,
197 mode.timing.pixel_clock = strtol(argv[optind], NULL, 0) * 1000;

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