Searched refs:MCInstrDesc (Results 151 - 175 of 206) sorted by relevance

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/freebsd-current/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp515 const MCInstrDesc &DefDesc = DefMI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/
H A DTailDuplicator.cpp1040 const MCInstrDesc &CopyD = TII->get(TargetOpcode::COPY);
H A DMachineLICM.cpp44 #include "llvm/MC/MCInstrDesc.h"
1311 const MCInstrDesc &MID = TII->get(NewOpc);
H A DMachineVerifier.cpp70 #include "llvm/MC/MCInstrDesc.h"
1029 const MCInstrDesc &MCID = MI->getDesc();
1856 const MCInstrDesc &MCID = MI->getDesc();
2095 const MCInstrDesc &MCID = MI->getDesc();
2141 report("Tied def doesn't match MCInstrDesc", MO, MONum);
H A DTwoAddressInstructionPass.cpp51 #include "llvm/MC/MCInstrDesc.h"
1327 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGISel.cpp87 #include "llvm/MC/MCInstrDesc.h"
672 const MCInstrDesc &MCID = TII->get(MI.getOpcode());
1306 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
4051 const MCInstrDesc &MCID = TII->get(TargetOpc);
4192 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64RegisterInfo.cpp778 const MCInstrDesc &MCID = TII->get(AArch64::ADDXri);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIShrinkInstructions.cpp252 const MCInstrDesc &NewDesc = TII->get(SOPKOpc);
H A DGCNHazardRecognizer.cpp816 const MCInstrDesc &Desc = MI.getDesc();
2850 const MCInstrDesc &InstDesc = I.getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp2881 const MCInstrDesc *NewD = (Ps & P::Zero) ?
2897 const MCInstrDesc *NewD;
3019 const MCInstrDesc &D = (V >= 0) ? HII.get(Hexagon::M2_macsip)
3161 const MCInstrDesc &JD = HII.get(Hexagon::J2_jump);
H A DHexagonGenInsert.cpp1398 const MCInstrDesc &D = R32 ? HII->get(Hexagon::S2_insert)
/freebsd-current/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp499 const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp436 const MCInstrDesc &Desc = MI.getDesc();
H A DARMConstantIslandPass.cpp43 #include "llvm/MC/MCInstrDesc.h"
2238 const MCInstrDesc &MCID = MI->getDesc();
2434 const MCInstrDesc &MCID = MI->getDesc();
/freebsd-current/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h133 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp26 #include "llvm/MC/MCInstrDesc.h"
728 bool hasForbiddenSlot(const MCInstrDesc &MCID) const {
732 bool SafeInForbiddenSlot(const MCInstrDesc &MCID) const {
1840 static bool needsExpandMemInst(MCInst &Inst, const MCInstrDesc &MCID) {
1877 const MCInstrDesc &MCID = MII.get(Opcode);
2736 const MCInstrDesc &MCID = MII.get(JalrInst.getOpcode());
3674 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
3765 const MCInstrDesc &Desc = MII.get(OpCode);
3892 const MCInstrDesc &Desc = MII.get(OpCode);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEFrameLowering.cpp213 const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp24 #include "llvm/MC/MCInstrDesc.h"
202 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp31 #include "llvm/MC/MCInstrDesc.h"
74 MCInstrDesc Insts[4445];
2493 const MCInstrDesc &MCID =
7490 static int findFirstVectorPredOperandIdx(const MCInstrDesc &MCID) {
7498 static bool isVectorPredicable(const MCInstrDesc &MCID) {
7518 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10901 const MCInstrDesc &MCID = MII.get(Opc);
11024 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
11057 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
11081 const MCInstrDesc
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/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp635 const MCInstrDesc &Desc = TII.get(Opc);
2774 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
4039 const MCInstrDesc &II = TII.get(MachineInstOpcode);
H A DX86SpeculativeLoadHardening.cpp846 const MCInstrDesc &MCID = TII.get(UnfoldedOpc);
/freebsd-current/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXReplaceImageHandles.cpp1743 const MCInstrDesc &MCID = MI.getDesc();
/freebsd-current/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp262 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
/freebsd-current/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1838 const MCInstrDesc &MCID = get(Opc);
2047 const MCInstrDesc &UseMCID = UseMI.getDesc();
2715 const MCInstrDesc &NewDesc = get(NewOpC);
2805 const MCInstrDesc &NewDesc = get(NewOpC);
/freebsd-current/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp109 const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
188 // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been

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