Searched refs:isReg (Results 26 - 50 of 347) sorted by relevance

1234567891011>>

/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineInstr.cpp164 if (MO.isReg())
173 if (MO.isReg())
220 bool isImpReg = Op.isReg() && Op.isImplicit();
222 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
268 if (NewMO->isReg()) {
303 if (Operands[i].isReg())
308 if (MRI && Operands[OpNo].isReg())
618 if (!MO.isReg()) {
685 if (!MO.isReg() || !MO.isDef())
732 if (MO.isReg()
[all...]
H A DLivePhysRegs.cpp60 if (!MOP.isReg() || !MOP.readsReg())
84 if (O->isReg() && !O->isDebug()) {
106 if (Reg.second->isReg() && Reg.second->isDead())
289 if (!MO->isReg() || !MO->isDef() || MO->isDebug())
318 if (!MO->isReg() || !MO->readsReg() || MO->isDebug())
H A DImplicitNullChecks.cpp279 if (!(MOA.isReg() && MOA.getReg()))
284 if (!(MOB.isReg() && MOB.getReg()))
372 !BaseOp->isReg() || BaseOp->getReg() != PointerReg)
423 if (!(DependenceMO.isReg() && DependenceMO.getReg()))
484 if (!(MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
608 return MO.isReg() && MO.getReg() && MO.isDef() &&
650 if (MO.isReg()) {
697 if (!MO.isReg() || !MO.isDef())
707 if (!MO.isReg() || !MO.getReg() || !MO.isDef() || MO.isDead())
H A DMachineSink.cpp436 if (MO.isReg() && MO.getReg().isVirtual())
466 if (!MO.isReg() || !MO.isUse())
664 if (!MO.isReg()) continue; // Ignore non-register operands.
778 if (!BaseOp->isReg())
788 return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 &&
923 if (!MO.isReg()) continue;
996 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
1030 if (MO.isReg() && MO.isUse())
1040 assert(MI.getOperand(1).isReg());
1048 if (!MO.isReg() || !M
[all...]
H A DProcessImplicitDefs.cpp70 if (MO.isReg() && MO.isUse() && MO.readsReg())
102 if (!MO.isReg())
H A DMachineInstrBundle.cpp64 if (MO.isReg() && MO.isInternalRead())
151 if (!MO.isReg())
287 if (!MO.isReg() || MO.getReg() != Reg)
325 if (!MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DAntiDepBreaker.h63 if (MI.getDebugOperand(0).isReg() &&
H A DLiveVariables.h218 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
254 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/MC/MCParser/
H A DMCParsedAsmOperand.h58 /// isReg - Is this a register operand?
59 virtual bool isReg() const = 0;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcInstPrinter.cpp64 if (!MI->getOperand(0).isReg())
88 || (!MI->getOperand(0).isReg())
114 if (MO.isReg()) {
154 if (MO.isReg() && MO.getReg() == SP::G0)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp115 assert(Target->isReg());
116 assert(Replaced->isReg());
272 assert(To.isReg() && From.isReg());
284 return LHS.isReg() &&
285 RHS.isReg() &&
292 if (!Reg->isReg() || !Reg->isDef())
314 if (!Reg->isReg())
322 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())
373 assert(Src && (Src->isReg() || Sr
[all...]
H A DSIShrinkInstructions.cpp79 if (Src0.isReg()) {
177 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
185 if (!MI.getOperand(0).isReg())
190 if (!Src0.isReg())
285 if (MI.getOperand(i).isReg() && MI.getOperand(i).isTied() &&
370 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) {
376 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
399 if (!MO.isReg())
469 if (!Xop.isReg())
489 !MovY->getOperand(1).isReg() ||
[all...]
H A DSIPreAllocateWWMRegs.cpp91 if (!MO.isReg())
125 if (!MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonNewValueJump.cpp152 if (!Op.isReg() || !Op.isDef())
177 if (II->getOperand(i).isReg() &&
566 if (foundJump && !foundCompare && MI.getOperand(0).isReg() &&
573 isSecondOpReg = MI.getOperand(2).isReg();
602 if (MI.getOperand(0).isReg() && MI.getOperand(0).isDef() &&
653 if (!MO.isReg() || !MO.isUse())
660 if (!Op.isReg() || !Op.isUse() || !Op.isKill())
706 if (cmpInstr->getOperand(0).isReg() &&
709 if (cmpInstr->getOperand(1).isReg() &&
H A DHexagonGenMux.cpp172 if (!MO.isReg() || MO.isImplicit())
210 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register();
371 if (!Op.isReg() || !Op.isUse())
H A DHexagonVLIWPacketizer.cpp151 if (!MO.isReg() || !MO.isDef())
321 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
396 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
438 if (MO.isReg() && MO.getReg() == DestReg)
586 if (MO.isReg() && MO.isDef())
590 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
596 assert(Op1.isReg() && "Post increment operand has be to a register.");
602 assert(Op0.isReg() && "Post increment operand has be to a register.");
660 if (Val.isReg() && Val.getReg() != DepReg)
713 if (!MO.isReg())
[all...]
H A DHexagonHazardRecognizer.cpp51 if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
116 if (MO.isReg() && MO.isDef() && !MO.isImplicit())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRAsmPrinter.cpp98 assert(RegOp.isReg() && "Operand must be a register when you're"
145 assert(MO.isReg() && "Unexpected inline asm memory operand");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRInstPrinter.cpp123 if (Op.isReg()) {
175 assert(MI->getOperand(OpNo).isReg() && "Expected a register for the first operand");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp90 if (MO.isReg())
163 assert(Op1.isReg() && "First operand is not register.");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARC/MCTargetDesc/
H A DARCInstPrinter.cpp143 if (Op.isReg()) {
161 assert(base.isReg() && "Base should be register.");
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVAsmPrinter.cpp121 if (!MO.isReg())
157 if (!MO.isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEMCCodeEmitter.cpp103 if (MO.isReg())
130 if (MO.isReg() || MO.isImm())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCInst.cpp24 else if (isReg())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIChecking.cpp115 if (!MO.isReg() || MO.isUse())

Completed in 371 milliseconds

1234567891011>>