Searched refs:isDef (Results 76 - 100 of 167) sorted by relevance
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | ShrinkWrap.cpp | 280 if (!MO.isDef() && !MO.readsReg())
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| H A D | ExecutionDomainFix.cpp | 387 if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx] != dv)) {
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| H A D | RegisterCoalescer.cpp | 1231 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
1374 if (MO.isReg() && MO.isDef()) {
1636 if (MO.isDef() /*|| MO.isUndef()*/)
1666 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
1676 if (MO.isDef())
1747 if (SubIdx && MO.isDef())
2455 if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
2889 if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
3006 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
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| H A D | MIRPrinter.cpp | 743 for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
893 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
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| H A D | EarlyIfConversion.cpp | 266 if (MO.isDef() && Register::isPhysicalRegister(Reg))
387 if (MO.isDef())
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| H A D | RDFGraph.cpp | 611 if (Op.isDef() && Op.isDead())
637 const MCPhysReg *ImpR = Op.isDef() ? D.getImplicitDefs()
1294 if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
1339 if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
1554 if (RA.Addr->isDef())
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| H A D | MachineVerifier.cpp | 1573 else if (!MO->isDef() && !MCOI.isOptionalDef())
1584 if (MO->isDef() && !MCOI.isOptionalDef() && !MCID.variadicOpsAreDefs())
1968 if (LI.hasSubRanges() && !MO->isDef()) {
2047 if (MO->isDef()) {
2335 if (!MODef.isReg() || !MODef.isDef()) {
2558 if (!MOI->isReg() || !MOI->isDef())
2703 if (MOI->isDef()) {
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| H A D | LiveDebugValues.cpp | 1238 if (MO.isReg() && MO.isDef() && MO.getReg() &&
1463 if (!DestRegOp->isDef())
1765 if (MO.isReg() && MO.isDef() && MO.getReg())
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| H A D | TwoAddressInstructionPass.cpp | 259 if (MO.isDef() && DI->second > LastDef)
767 if (MO.isDef())
811 if (MO.isDef()) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonGenMux.cpp | 175 BitVector &Set = MO.isDef() ? Defs : Uses;
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| H A D | HexagonBitTracker.cpp | 196 if (!MO.isReg() || !MO.isDef())
1043 if (!Op.isReg() || !Op.isDef())
1190 assert(MD.isReg() && MD.isDef());
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CSEInfo.cpp | 373 if (!MO.isDef())
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURewriteOutArguments.cpp | 309 if (Q.isDef())
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| H A D | R600MachineScheduler.cpp | 366 if (MO.isReg() && !MO.isDef() &&
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| H A D | SILowerControlFlow.cpp | 160 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
209 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 335 if (MO.isDef()) {
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| H A D | WebAssemblyRegStackify.cpp | 87 /*isDef=*/true,
93 /*isDef=*/false,
395 if (!MO.isDef() && !MRI.hasOneDef(Reg))
428 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CallFrameOptimization.cpp | 343 if (MO.isDef()) {
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| H A D | X86FlagsCopyLowering.cpp | 430 assert(DOp.isDef() && "Expected register def!");
744 assert(MI.getOperand(0).isDef() &&
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| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 517 if (MO.isDef() && MO.isImplicit())
1456 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | GICombinerEmitter.cpp | 428 if (InstrOperand.isDef()) {
436 if (InstrOperand.isDef()) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 209 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
777 bool isDef = isLoadSingle(Opcode); local
825 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
881 if (!MO.isReg() || !MO.isDef() || MO.isDead())
950 else if (MO.isDef())
1663 bool isDef, unsigned NewOpc, unsigned Reg,
1668 if (isDef) {
2173 if (MO.isDef() && TRI->regsOverlap(Reg, Base))
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| H A D | Thumb2SizeReduction.cpp | 310 if (!MO.isReg() || MO.isUndef() || MO.isDef())
1000 if (!MO.isReg() || MO.isUndef() || MO.isDef())
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 366 if (MO.isDef()) {
483 if (MO.isDef() && !MO.isDead())
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsDelaySlotFiller.cpp | 330 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
420 if (checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef())) {
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Completed in 404 milliseconds
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