/freebsd-13-stable/sys/crypto/openssl/arm/ |
H A D | ghashv8-armx.S | 16 vshl.i64 q11,q11,#57 @ 0xc2.0 24 vshl.i64 q3,q3,#1
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/freebsd-13-stable/crypto/openssl/crypto/bn/asm/ |
H A D | armv4-mont.pl | 336 vshl.i64 $Ni,@ACC[0]#hi,#16 385 vshl.i64 $Ni,@ACC[0]#hi,#16 478 vshl.i64 $Ni,@ACC[0]#hi,#16 515 vshl.i64 $Ni,@ACC[0]#hi,#16
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUTargetTransformInfo.cpp | 474 if (SLT == MVT::i64) 487 if (SLT == MVT::i64) { 498 if (SLT == MVT::i64) {
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H A D | SIISelLowering.cpp | 129 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); 231 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 234 setOperationAction(ISD::SELECT, MVT::i64, Custom); 236 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64); 240 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 270 setOperationAction(ISD::BR_CC, MVT::i64, Expand); 280 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 281 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 282 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 285 setOperationAction(ISD::ADDCARRY, MVT::i64, Lega [all...] |
H A D | AMDGPUISelDAGToDAG.cpp | 729 // We are selecting i64 ADD here instead of custom lower it during 730 // DAG legalization, so we can fold some i64 ADDs used for address 736 if (N->getValueType(0) != MVT::i64) 791 } else if (N->getValueType(0) == MVT::i64) { 1027 MVT::i64, RegSequenceArgs); 1633 if (Addr.getValueType() == MVT::i64 && Addr.getOpcode() == ISD::BITCAST && 1636 // (i64 (bitcast (v2i32 (build_vector 1754 MVT::i64, RegSequenceArgs), 1854 return SDValue(CurDAG->getMachineNode(AMDGPU::REG_SEQUENCE, SL, MVT::i64, 2101 if (VT == MVT::i64) { [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 503 // i64 conversions are done via library routines even when generating VFP 515 // i64 conversions are done via library routines even when generating VFP 773 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom); 774 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom); 1103 // i64 operation support. 1104 setOperationAction(ISD::MUL, MVT::i64, Expand); 1117 setOperationAction(ISD::SRL, MVT::i64, Custom); 1118 setOperationAction(ISD::SRA, MVT::i64, Custom); 1120 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 1121 setOperationAction(ISD::LOAD, MVT::i64, Custo [all...] |
/freebsd-13-stable/sys/dev/bhnd/nvram/ |
H A D | bhnd_nvram_value_prf.c | 630 int64_t i64; member in union:__anon11630
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 735 MVT::i64, GlobalVal)); 824 case MVT::i64: 1667 // i32,ch = load<LD1[%data1(addrspace=1)], zext from i8> t0, t7, undef:i64 3562 } else if (Val.getValueType() == MVT::i64) { 3629 return SelectADDRsi_imp(OpNode, Addr, Base, Offset, MVT::i64); 3672 return SelectADDRri_imp(OpNode, Addr, Base, Offset, MVT::i64); 3729 case MVT::i64: 3740 case MVT::i64: 3751 case MVT::i64: 3754 case MVT::i64 [all...] |
/freebsd-13-stable/contrib/ntp/ntpd/ |
H A D | ntp_timer.c | 252 DueTime.QuadPart = Period * 10000i64;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 145 // Re-assemble i64 arguments split up in SelectionDAGBuilder's 153 // TODO: fix inline asm support so I can simply tell it that 'i64' 162 // Normally, i64 data is bounded to two arbitrary GPRs for "%r" 344 if (N->getValueType(0) == MVT::i64)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyAsmPrinter.cpp | 60 for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
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H A D | WebAssemblyExplicitLocals.cpp | 160 return MVT::i64;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16ISelLowering.cpp | 145 setOperationAction(ISD::ROTR, MVT::i64, Expand); 147 setOperationAction(ISD::BSWAP, MVT::i64, Expand);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64CallLowering.cpp | 413 RegParmTypes.push_back(MVT::i64); 425 Forwards.push_back(ForwardedRegister(X8VReg, AArch64::X8, MVT::i64));
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
H A D | AVRISelLowering.cpp | 78 setOperationAction(ISD::ADD, MVT::i64, Custom); 100 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 106 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand); 110 setOperationAction(ISD::SETCC, MVT::i64, Custom); 555 } else if (VT == MVT::i64) {
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/freebsd-13-stable/sys/contrib/openzfs/module/os/linux/spl/ |
H A D | spl-kstat.c | 155 seq_printf(f, "%lld", (signed long long)knp->value.i64);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.h | 182 // Create a vector from two i64 GPRs. 452 return VT == MVT::i32 || VT == MVT::i64;
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/freebsd-13-stable/crypto/openssl/crypto/modes/asm/ |
H A D | ghashv8-armx.pl | 100 vshl.i64 $xC2,$xC2,#57 @ 0xc2.0 108 vshl.i64 $IN,$IN,#1
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLoweringHVX.cpp | 73 setOperationAction(ISD::BITCAST, MVT::i64, Custom); 596 ? DAG.getUNDEF(MVT::i64) 597 : DAG.getNode(HexagonISD::P2D, dl, MVT::i64, PredV); 850 SDValue WW = DAG.getNode(HexagonISD::COMBINE, dl, MVT::i64, {W1, W0}); 981 SDValue V = DAG.getBitcast(MVT::i64, SubV); 1566 HexagonISD::COMBINE, dl, MVT::i64, {Words[i+1], Words[i]});
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 304 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 454 if (TLI.isTypeLegal(MVT::i64)) { 456 zextOrTrunc(64), SDLoc(CFP), MVT::i64); 1095 // READCYCLECOUNTER returns an i64, even if type legalization might have 1097 Action = TLI.getOperationAction(Node->getOpcode(), MVT::i64); 2141 case MVT::i64: LC = Call_I64; break; 2198 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 2427 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2430 if ((SrcVT == MVT::i32 || SrcVT == MVT::i64) && DestVT == MVT::f32) { 2431 LLVM_DEBUG(dbgs() << "Converting unsigned i32/i64 t [all...] |
H A D | LegalizeIntegerTypes.cpp | 15 // implementing i64 arithmetic in two i32 registers (often needed on 32-bit 2632 // For example, extension of an i48 to an i64. The operand type necessarily 3073 else if (VT == MVT::i64) 3441 else if (VT == MVT::i64) 3519 else if (VT == MVT::i64) 3529 else if (VT == MVT::i64) 3540 else if (VT == MVT::i64) 3572 // For example, extension of an i48 to an i64. The operand type necessarily 3601 // things like sextinreg V:i64 from i8. 3606 // For example, extension of an i48 to an i64 [all...] |
/freebsd-13-stable/sys/contrib/openzfs/cmd/zpool/ |
H A D | zpool_main.c | 9508 uint64_t i64; local 9560 (void) nvpair_value_int64(nvp, (void *)&i64); 9561 printf(gettext("0x%llx"), (u_longlong_t)i64); 9565 (void) nvpair_value_uint64(nvp, &i64); 9575 zpool_state_to_name(i64, VDEV_AUX_NONE), 9576 (u_longlong_t)i64); 9578 printf(gettext("0x%llx"), (u_longlong_t)i64); 9583 (void) nvpair_value_hrtime(nvp, (void *)&i64); 9584 printf(gettext("0x%llx"), (u_longlong_t)i64);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 260 return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64); 389 return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64); 426 return isSCSrcB64() || isLiteralImm(MVT::i64); 456 return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64); 488 return isVCSrcF64() || isLiteralImm(MVT::i64); 1580 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand 1602 if (type == MVT::f64 || type == MVT::i64) { // Expected 64-bit operand 1653 if (type == MVT::i64) { // Expected 64-bit int operand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 187 case MVT::i64: return Type::getInt64Ty(Context);
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/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 65 case MVT::i64: return "MVT::i64";
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