| /freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstPrinter.cpp | 106 return Opnd.isReg() && MRI.getRegClass(C.Value).contains(Opnd.getReg());
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| /freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 68 RCs.push_back(RegisterClassHierarchy.getRegClass(RCDef));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 286 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) {
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| H A D | AVRISelDAGToDAG.cpp | 219 RI.getRegClass(RegNode->getReg()) == &AVR::PTRDISPREGSRegClass) {
265 if (RI.getRegClass(Reg) != &AVR::PTRDISPREGSRegClass) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPeephole.cpp | 241 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
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| H A D | HexagonVExtract.cpp | 139 const auto &VecRC = *MRI.getRegClass(VecR);
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| H A D | HexagonGenInsert.cpp | 686 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
687 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR);
688 const TargetRegisterClass *InsRC = MRI->getRegClass(InsR);
1406 const TargetRegisterClass *RC = MRI->getRegClass(VR);
1419 bool R32 = MRI->getRegClass(NewR) == &Hexagon::IntRegsRegClass;
1425 if (R32 && MRI->getRegClass(IF.InsR) == &Hexagon::DoubleRegsRegClass) {
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsOptimizePICCall.cpp | 139 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | BreakFalseDeps.cpp | 135 TII->getRegClass(MI->getDesc(), OpIdx, TRI, *MF);
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| H A D | RegAllocGreedy.cpp | 704 const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
915 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
916 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
1120 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
1683 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2005 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
2070 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2514 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2533 MRI->getRegClass(Intf->reg) == CurRC) &&
2928 if (CurrPhys != PhysReg && (!MRI->getRegClass(Re
[all...] |
| H A D | RegAllocFast.cpp | 256 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
322 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
348 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
668 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
762 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
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| H A D | InlineSpiller.cpp | 414 MRI.getRegClass(SrcReg), &TRI);
922 MRI.getRegClass(NewVReg), &TRI);
958 MRI.getRegClass(NewVReg), &TRI);
1082 StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original));
1135 << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
1521 MRI.getRegClass(LiveReg), &TRI);
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| H A D | CriticalAntiDepBreaker.cpp | 192 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
319 NewRC = TII->getRegClass(MI.getDesc(), i, TRI, MF);
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| H A D | MachineLICM.cpp | 910 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1354 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
1449 OrigRCs.push_back(MRI->getRegClass(DupReg));
1451 if (!MRI->constrainRegClass(DupReg, MRI->getRegClass(Reg))) {
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| H A D | MachineSSAUpdater.cpp | 61 VRC = MRI->getRegClass(VR);
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| H A D | CalcSpillWeights.cpp | 72 const TargetRegisterClass *rc = mri.getRegClass(reg);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64DeadRegisterDefinitionsPass.cpp | 160 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64RegisterBankInfo.cpp | 67 assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
73 assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
75 assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
80 assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/ |
| H A D | VEInstPrinter.cpp | 42 if (MRI.getRegClass(VE::MISCRegClassID).contains(RegNo))
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyRegStackify.cpp | 106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
538 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
574 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(Reg));
645 const auto *RegClass = MRI.getRegClass(Reg);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 416 const TargetRegisterClass *RC = MRI->getRegClass(OpInfo.Regs.front());
465 In = MRI->createVirtualRegister(MRI->getRegClass(Def));
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| H A D | CSEMIRBuilder.cpp | 62 B.addNodeIDRegType(Op.getRegClass());
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 548 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
574 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
1037 .getRegClass(MI.getOperand(OpNum).getReg())) &&
1195 const TargetRegisterClass *RC = TRI->getRegClass(MCOI.RegClass);
1305 if (MRI.getRegClass(Reg) == &SystemZ::VR32BitRegClass)
1307 else if (MRI.getRegClass(Reg) == &SystemZ::VR64BitRegClass)
1309 else if (MRI.getRegClass(Reg) == &SystemZ::VR128BitRegClass)
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVEVPTOptimisationsPass.cpp | 155 Register NewResult = MRI->createVirtualRegister(MRI->getRegClass(Target));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 162 if (MRI->getRegClass(DstReg) == &BPF::GPR32RegClass) {
|