/freebsd-13-stable/sys/riscv/riscv/ |
H A D | swtch.S | 73 fsd f16, (PCB_X + 16 * 16)(\p) 122 fld f16, (PCB_X + 16 * 16)(\p) 184 fcvt.d.l f16, zero
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/freebsd-13-stable/contrib/llvm-project/lldb/source/Plugins/Process/Utility/ |
H A D | RegisterInfos_ppc64.h | 112 DEFINE_FPR_PPC64(f16, NULL, LLDB_INVALID_REGNUM), \ 258 uint64_t f16; member in struct:_FPR_PPC64
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H A D | RegisterContextFreeBSD_powerpc.cpp | 114 uint64_t f16; member in struct:_FPR
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H A D | RegisterContext_mips.h | 303 uint64_t f16; member in struct:FPR_linux_mips
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H A D | RegisterInfos_ppc64le.h | 123 DEFINE_FPR(f16, NULL, LLDB_INVALID_REGNUM), \ 336 uint64_t f16; member in struct:_FPR
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H A D | RegisterInfos_powerpc.h | 102 DEFINE_FPR(f16, LLDB_INVALID_REGNUM), \
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H A D | RegisterInfos_mips.h | 179 DEFINE_FPR(f16, nullptr, dwarf_f16_mips, dwarf_f16_mips,
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H A D | RegisterInfos_mips64.h | 305 DEFINE_FPR(f16, nullptr, dwarf_f16_mips64, dwarf_f16_mips64,
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/freebsd-13-stable/contrib/llvm-project/compiler-rt/lib/tsan/rtl/ |
H A D | tsan_rtl_ppc64.S | 70 stfd f16,192(r3) 215 stfd f16,192(r3)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 146 addRegisterClass(MVT::f16, &AArch64::FPR16RegClass); 251 setOperationAction(ISD::SETCC, MVT::f16, Custom); 254 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom); 257 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom); 265 setOperationAction(ISD::BR_CC, MVT::f16, Custom); 270 setOperationAction(ISD::SELECT, MVT::f16, Custom); 275 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom); 440 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Custom); 442 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); 444 setOperationAction(ISD::FREM, MVT::f16, Promot [all...] |
H A D | AArch64CallingConvention.cpp | 95 else if (LocVT.SimpleTy == MVT::f16)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 167 addRegisterClass(MVT::f16, &AMDGPU::SReg_32RegClass); 451 setOperationAction(ISD::FPOW, MVT::f16, Promote); 452 setOperationAction(ISD::FLOG, MVT::f16, Custom); 453 setOperationAction(ISD::FEXP, MVT::f16, Custom); 454 setOperationAction(ISD::FLOG10, MVT::f16, Custom); 567 setOperationAction(ISD::ConstantFP, MVT::f16, Legal); 570 setOperationAction(ISD::LOAD, MVT::f16, Promote); 571 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16); 572 setOperationAction(ISD::STORE, MVT::f16, Promote); 573 AddPromotedToType(ISD::STORE, MVT::f16, MV [all...] |
H A D | AMDGPUISelLowering.cpp | 174 setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand); 188 setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand); 258 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 266 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 703 (ScalarVT == MVT::f16 && Subtarget->has16BitInsts())); 843 (Subtarget->has16BitInsts() && VT == MVT::f16); 849 (Subtarget->has16BitInsts() && VT == MVT::f16) || 2497 if (DestVT == MVT::f16) 2508 if (Subtarget->has16BitInsts() && DestVT == MVT::f16) { 2514 DAG.getNode(ISD::FP_ROUND, DL, MVT::f16, IntToFp3 [all...] |
/freebsd-13-stable/contrib/llvm-project/libunwind/src/ |
H A D | UnwindRegistersSave.S | 179 sdc1 $f16, (4 * 36 + 8 * 16)($4) 204 sdc1 $f16, (4 * 36 + 8 * 16)($4) 295 sdc1 $f16, (8 * 51)($4) 628 stfd %f16,288(%r3) 1083 fsd f16, (8 * 32 + 8 * 16)(a0)
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/freebsd-13-stable/crypto/openssl/crypto/perlasm/ |
H A D | sparcv9_modes.pl | 687 aes_eround01 %f16, %f14, %f2, %f4 691 camellia_f %f16, %f2, %f14, %f2 768 aes_eround01 %f16, %f14, %f2, %f8 770 aes_eround01 %f16, %f14, %f6, %f10 774 camellia_f %f16, %f2, %f14, %f2 775 camellia_f %f16, %f6, %f14, %f6 873 aes_eround01 %f16, %f14, %f2, %f8 875 aes_eround01 %f16, %f14, %f6, %f10 879 camellia_f %f16, %f2, %f14, %f2 880 camellia_f %f16, [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 522 // There's no way to specify FP16 immediates in .f16 ops, so we have to 523 // load them into an .f16 register first. 525 if (N->getValueType(0) != MVT::f16) 528 cast<ConstantFPSDNode>(N)->getValueAPF(), SDLoc(N), MVT::f16); 530 CurDAG->getMachineNode(NVPTX::LOAD_CONST_F16, SDLoc(N), MVT::f16, Val); 644 // Merge (f16 extractelt(V, 0), f16 extractelt(V,1)) 645 // into f16,f16 SplitF16x2(V) 647 CurDAG->getMachineNode(Op, SDLoc(N), MVT::f16, MV [all...] |
/freebsd-13-stable/crypto/openssl/crypto/ |
H A D | ia64cpuid.S | 119 { .mfi; mov f16=f0 }
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMCallingConv.cpp | 211 case MVT::f16: 298 // f16 arguments are extended to i32 and assigned to a register in [r0, r3] 307 // f16 arguments are extended to f32 and assigned to a register in [s0, s15]
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H A D | ARMISelLowering.cpp | 741 addRegisterClass(MVT::f16, &ARM::HPRRegClass); 743 setOperationAction(ISD::BITCAST, MVT::f16, Custom); 745 setOperationAction(ISD::FMINNUM, MVT::f16, Legal); 746 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal); 1039 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom); 1040 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom); 1054 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand); 1059 setTruncStoreAction(MVT::f32, MVT::f16, Expand); 1060 setTruncStoreAction(MVT::f64, MVT::f16, Expand); 1354 setOperationAction(ISD::SETCC, MVT::f16, Expan [all...] |
/freebsd-13-stable/sys/mips/mips/ |
H A D | fp.S | 2320 mfc1 t2, $f16 2418 mfc1 ta0, $f16 2516 mfc1 t0, $f16 2628 mfc1 ta3, $f16 2743 mfc1 t3, $f16 2853 mfc1 t0, $f16 2931 mfc1 ta0, $f16 3039 mfc1 t3, $f16 3133 mfc1 ta3, $f16 3250 mtc1 t2, $f16 [all...] |
/freebsd-13-stable/crypto/openssl/crypto/poly1305/asm/ |
H A D | poly1305-ppcfp.pl | 240 stfd f16,`$FRAME-8*16`($sp) 522 lfd f16,`$FRAME-8*16`($sp)
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/freebsd-13-stable/crypto/openssl/crypto/sha/asm/ |
H A D | sha1-sparcv9a.pl | 87 "%f8", "%f9","%f10","%f11","%f12","%f13","%f14","%f15","%f16"); 473 fpadd32 $VK_00_19,@X[0],%f16 481 std %f16,[$Xfer+0]
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | ValueTypes.cpp | 189 case MVT::f16: return Type::getHalfTy(Context); 485 case Type::HalfTyID: return MVT(MVT::f16);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
H A D | AMDGPUAsmParser.cpp | 264 return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16); 395 return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16); 438 return isSCSrcB16() || isLiteralImm(MVT::f16); 476 return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16); 508 return isVCSrcF16() || isLiteralImm(MVT::f16); 532 return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16); 556 return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16); 580 return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16); 604 return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16); 628 return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16); [all...] |
/freebsd-13-stable/crypto/openssl/crypto/bn/asm/ |
H A D | ia64-mont.pl | 378 ni0=f16; ni1=f17; ni2=f18; ni3=f19; ni4=f20; ni5=f21; ni6=f22; ni7=f23; 398 stf.spill [sp]=f16,-16 844 { .mmi; ldf.fill f16=[r16],64
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