Lines Matching refs:f16
741 addRegisterClass(MVT::f16, &ARM::HPRRegClass);
743 setOperationAction(ISD::BITCAST, MVT::f16, Custom);
745 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
746 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
1039 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
1040 setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Custom);
1054 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
1059 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
1060 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
1354 setOperationAction(ISD::SETCC, MVT::f16, Expand);
1355 setOperationAction(ISD::SELECT, MVT::f16, Custom);
1356 setOperationAction(ISD::SELECT_CC, MVT::f16, Custom);
1364 setOperationAction(ISD::BR_CC, MVT::f16, Custom);
1393 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
1399 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
1406 setOperationAction(ISD::STRICT_FSETCC, MVT::f16, Custom);
1407 setOperationAction(ISD::STRICT_FSETCCS, MVT::f16, Custom);
1452 setOperationAction(ISD::FREM, MVT::f16, Promote);
1453 setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
1454 setOperationAction(ISD::FSIN, MVT::f16, Promote);
1455 setOperationAction(ISD::FCOS, MVT::f16, Promote);
1456 setOperationAction(ISD::FSINCOS, MVT::f16, Promote);
1457 setOperationAction(ISD::FPOWI, MVT::f16, Promote);
1458 setOperationAction(ISD::FPOW, MVT::f16, Promote);
1459 setOperationAction(ISD::FEXP, MVT::f16, Promote);
1460 setOperationAction(ISD::FEXP2, MVT::f16, Promote);
1461 setOperationAction(ISD::FLOG, MVT::f16, Promote);
1462 setOperationAction(ISD::FLOG10, MVT::f16, Promote);
1463 setOperationAction(ISD::FLOG2, MVT::f16, Promote);
1465 setOperationAction(ISD::FROUND, MVT::f16, Legal);
1476 setOperationAction(ISD::FMINIMUM, MVT::f16, Legal);
1477 setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal);
2144 // f16 arguments have their size extended to 4 bytes and passed as if they
2148 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
2319 // f16 arguments have their size extended to 4 bytes and passed as if they
2323 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16)) {
2326 // f16 arguments could have been extended prior to argument lowering.
2329 if (isCmseNSCall && (ArgVT == MVT::f16)) {
2975 // t11 f16 = fadd ...
2981 // that produces the f16 value, t11 in this case.
3004 // Mask f16 arguments if this is a CMSE nonsecure entry.
3006 if (AFI->isCmseNSEntryFunction() && (RetVT == MVT::f16)) {
3007 if (VA.needsCustom() && VA.getValVT() == MVT::f16) {
4197 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4214 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
4326 if (RegVT == MVT::f16 || RegVT == MVT::bf16)
4374 // f16 arguments have their size extended to 4 bytes and passed as if they
4378 (VA.getValVT() == MVT::f16 || VA.getValVT() == MVT::bf16))
5158 if (VT == MVT::f16)
5281 if (Subtarget->hasFPARMv8Base() && (TrueVal.getValueType() == MVT::f16 ||
5305 // match CMPFPw0 instead of CMPFP, though we don't do this for f16 because we
5306 // must use VSEL (limited condition codes), due to not having conditional f16
5309 !(isFloatingPointZero(RHS) && TrueVal.getValueType() != MVT::f16) &&
5310 (TrueVal.getValueType() == MVT::f16 ||
5971 (DstVT == MVT::f16 || DstVT == MVT::bf16))
5976 (SrcVT == MVT::f16 || SrcVT == MVT::bf16))
7597 assert(FVT == MVT::f32 || FVT == MVT::f16);
8482 // INSERT_VECTOR_ELT doesn't want f16 operands promoting to f32,
13428 // t18: f16 = ARMISD::VMOVhr t5
13440 // fold (VMOVhr (load x)) -> (load (f16*)x)
13734 if (VT == MVT::f16 && X.getValueType() == MVT::i32)
13736 if (VT == MVT::i32 && X.getValueType() == MVT::f16)
14290 else if (Op.getValueType() == MVT::f16)
14437 if (FromEltVT == MVT::f32 && ToEltVT == MVT::f16)
14495 if (ToEltVT == MVT::f16) {
15193 if (ToEltVT == MVT::f32 && FromEltVT == MVT::f16)
15196 (FromEltVT != MVT::f16 && FromVT.getVectorNumElements() == NumElements) ||
15233 if (FromEltVT == MVT::f16) {
16249 // combiner rewrite fneg into xors and some other instructions. For f16 and
16254 case MVT::f16:
16471 case MVT::f16:
16535 case MVT::f16:
17829 MVT SrcVT = (Sz == 16 ? MVT::f16 : MVT::f32);
17938 if (VT == MVT::f16 && Subtarget->hasFullFP16())
18443 // Ensure the vector doesn't have f16 elements. Even though we could do an
18444 // i16 vldN, we can't hold the f16 vectors and will end up converting via