Searched refs:TII (Results 176 - 200 of 403) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ConditionOptimizer.cpp95 const TargetInstrInfo *TII; member in class:__anon3842::AArch64ConditionOptimizer
281 BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
293 BuildMI(*MBB, BrMI, BrMI.getDebugLoc(), TII->get(AArch64::Bcc))
334 TII = MF.getSubtarget().getInstrInfo();
350 if (TII->analyzeBranch(*HBB, TBB, FBB, HeadCond)) {
361 if (TII->analyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp471 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
502 TII.get(X86::AND8ri), AndResult)
639 const MCInstrDesc &Desc = TII.get(Opc);
684 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
1250 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
1269 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
1277 TII.get(Subtarget->is64Bit() ? X86::RETIQ : X86::RETIL))
1281 TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL));
1399 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII
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/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DVirtRegMap.h42 const TargetInstrInfo *TII; member in class:llvm::VirtRegMap
70 : MachineFunctionPass(ID), MRI(nullptr), TII(nullptr), TRI(nullptr),
H A DMachineSSAUpdater.h53 const TargetInstrInfo *TII; member in class:llvm::MachineSSAUpdater
H A DSwiftErrorValueTracking.h41 const TargetInstrInfo *TII; member in class:llvm::SwiftErrorValueTracking
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBasicBlockInfo.cpp55 BBI.Size += TII->getInstSizeInBytes(I);
86 Offset += TII->getInstSizeInBytes(*I);
H A DMLxExpansionPass.cpp50 const ARMBaseInstrInfo *TII; member in struct:__anon4057::MLxExpansion
218 if (TII->isFpMLxInstruction(DefMI->getOpcode())) {
253 if (TII->canCauseFpMLxStall(NextMI->getOpcode())) {
284 const MCInstrDesc &MCID1 = TII->get(MulOpc);
285 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
288 MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI, MF));
356 if (!TII->isFpMLxInstruction(MCID.getOpcode(),
374 TII = static_cast<const ARMBaseInstrInfo *>(Fn.getSubtarget().getInstrInfo());
H A DMVEVPTBlockPass.cpp40 const Thumb2InstrInfo *TII; member in class:__anon4060::MVEVPTBlock
268 MIBuilder = BuildMI(Block, MI, DL, TII->get(NewOpcode));
275 MIBuilder = BuildMI(Block, MI, DL, TII->get(ARM::MVE_VPST));
303 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
H A DThumbRegisterInfo.h51 const ARMBaseInstrInfo &TII) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXPeephole.cpp108 const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); local
112 BuildMI(MF, Root.getDebugLoc(), TII->get(Prev.getOpcode()),
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandISEL.cpp48 const TargetInstrInfo *TII; member in class:__anon4263::PPCExpandISEL
149 TII = MF->getSubtarget().getInstrInfo();
234 BuildMI(*MBB, (*I), dl, TII->get(isISEL8(**I) ? PPC::OR8 : PPC::OR))
311 BuildMI(*MBB, (*MI), dl, TII->get(isISEL8(**MI) ? PPC::OR8 : PPC::OR))
410 BuildMI(*MBB, BIL.back(), dl, TII->get(PPC::BC))
417 TII->get(PPC::B))
447 TII->get(isISEL8(*MI) ? PPC::ADDI8 : PPC::ADDI))
455 TII->get(isISEL8(*MI) ? PPC::ORI8 : PPC::ORI))
H A DPPCMIPeephole.cpp87 const PPCInstrInfo *TII; member in struct:__anon4275::PPCMIPeephole
149 TII = MF->getSubtarget<PPCSubtarget>().getInstrInfo();
170 getKnownLeadingZeroCount(MachineInstr *MI, const PPCInstrInfo *TII) { argument
214 if (TII->isZeroExtended(*MI))
228 assert(TII->isTOCSaveMI(*MI) && "Expecting a TOC save instruction here");
275 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
290 if (TII->convertToImmediateForm(MI)) {
333 Simplified |= TII->onlyFoldImmediate(UseMI, MI, MIDestReg);
348 if (TII->isTOCSaveMI(MI))
403 BuildMI(MBB, &MI, MI.getDebugLoc(), TII
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600RegisterInfo.cpp42 const R600InstrInfo *TII = ST.getInstrInfo();
64 TII->reserveIndirectRegisters(Reserved, MF, *this);
H A DR600OptimizeVectorRegisters.cpp98 const R600InstrInfo *TII = nullptr; member in class:__anon3963::R600VectorRegMerger
157 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
219 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG),
235 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
271 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
342 TII = ST.getInstrInfo();
356 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugFixup.cpp68 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local
120 Prev.DebugValue->getDebugLoc(), TII->get(WebAssembly::DBG_VALUE), false,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineFrameInfo.cpp188 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); local
189 unsigned FrameSetupOpcode = TII.getCallFrameSetupOpcode();
190 unsigned FrameDestroyOpcode = TII.getCallFrameDestroyOpcode();
199 unsigned Size = TII.getFrameSize(MI);
H A DTailDuplicator.cpp87 TII = MF->getSubtarget().getInstrInfo();
386 TII->get(TargetOpcode::CFI_INSTRUCTION)).addCFIIndex(
390 MachineInstr &NewMI = TII->duplicate(*PredBB, PredBB->end(), *MI);
442 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI);
447 TII->get(TargetOpcode::COPY), NewReg)
582 if (TII->analyzeBranch(TailBB, PredTBB, PredFBB, PredCond) &&
708 if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
735 if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond))
774 TII->removeBranch(*PredBB);
784 TII
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H A DCriticalAntiDepBreaker.h39 const TargetInstrInfo *TII; member in class:llvm::CriticalAntiDepBreaker
H A DFixupStatepointCallerSaved.cpp160 const TargetInstrInfo &TII; member in class:__anon3465::StatepointState
177 TII(*MF.getSubtarget().getInstrInfo()), MFI(MF.getFrameInfo()),
209 TII.storeRegToStackSlot(*MI.getParent(), MI, Reg, true /*is_Kill*/, FI,
219 MF.CreateMachineInstr(TII.get(MI.getOpcode()), MI.getDebugLoc(), true);
H A DLiveDebugVariables.cpp182 const TargetInstrInfo &TII,
342 const TargetInstrInfo &TII,
348 const TargetInstrInfo &TII,
367 LiveIntervals &LIS, const TargetInstrInfo &TII);
381 void emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII);
1169 const TargetInstrInfo &TII,
1201 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize,
1303 LiveIntervals &LIS, const TargetInstrInfo &TII,
1344 BuildMI(*MBB, I, getDebugLoc(), TII.get(TargetOpcode::DBG_VALUE),
1355 const TargetInstrInfo &TII) {
1168 rewriteLocations(VirtRegMap &VRM, const MachineFunction &MF, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, SpillOffsetMap &SpillOffsets) argument
1300 insertDebugValue(MachineBasicBlock *MBB, SlotIndex StartIdx, SlotIndex StopIdx, DbgVariableValue DbgValue, bool Spilled, unsigned SpillOffset, LiveIntervals &LIS, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) argument
1353 insertDebugLabel(MachineBasicBlock *MBB, SlotIndex Idx, LiveIntervals &LIS, const TargetInstrInfo &TII) argument
1362 emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const SpillOffsetMap &SpillOffsets) argument
1411 emitDebugLabel(LiveIntervals &LIS, const TargetInstrInfo &TII) argument
1425 const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo(); local
[all...]
H A DMachineOperand.cpp407 const auto *TII = MF.getSubtarget().getInstrInfo(); local
408 assert(TII && "expected instruction info");
409 auto Indices = TII->getSerializableTargetIndices();
418 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) { argument
419 auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
481 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII, argument
483 auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
523 const auto *TII = MF->getSubtarget().getInstrInfo(); local
524 assert(TII && "expected instruction info");
525 auto Flags = TII
790 const auto *TII = MF->getSubtarget().getInstrInfo(); local
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandPseudoInsts.cpp31 const RISCVInstrInfo *TII; member in class:__anon4295::RISCVExpandPseudo
67 TII = static_cast<const RISCVInstrInfo *>(MF.getSubtarget().getInstrInfo());
126 BuildMI(NewMBB, DL, TII->get(RISCV::AUIPC), DestReg)
128 BuildMI(NewMBB, DL, TII->get(SecondOpcode), DestReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMachineScheduler.cpp87 HazardRec = SchedStates[MBB] = new SystemZHazardRecognizer(TII, &SchedModel);
112 (TII->getBranchInfo(*I).isIndirect() ||
113 TII->getBranchInfo(*I).getMBBTarget() == MBB));
131 TII(static_cast<const SystemZInstrInfo *>
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp43 const BPFInstrInfo *TII; member in struct:__anon4079::BPFMIPeephole
86 TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
226 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg)
277 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), dst)
396 const BPFInstrInfo *TII; member in struct:__anon4081::BPFMIPeepholeTruncElim
441 TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
535 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::MOV_rr), DstReg)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp32 const TargetInstrInfo &TII,
43 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
50 Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
58 TII.get(TargetOpcode::COPY), ConstrainedReg)
63 TII.get(TargetOpcode::COPY), Reg)
81 MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
88 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
116 return constrainOperandRegClass(MF, TRI, MRI, TII, RBI, InsertPt, *RegClass,
121 const TargetInstrInfo &TII,
153 MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RB
31 constrainRegToClass(MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, Register Reg, const TargetRegisterClass &RegClass) argument
41 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const TargetRegisterClass &RegClass, const MachineOperand &RegMO) argument
79 constrainOperandRegClass( const MachineFunction &MF, const TargetRegisterInfo &TRI, MachineRegisterInfo &MRI, const TargetInstrInfo &TII, const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II, const MachineOperand &RegMO, unsigned OpIdx) argument
120 constrainSelectedInstRegOperands(MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
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