1//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10/// R600 implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "R600RegisterInfo.h"
15#include "AMDGPUTargetMachine.h"
16#include "R600Defines.h"
17#include "R600InstrInfo.h"
18#include "R600MachineFunctionInfo.h"
19#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
20
21using namespace llvm;
22
23#define GET_REGINFO_TARGET_DESC
24#include "R600GenRegisterInfo.inc"
25
26unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) {
27  static const uint16_t SubRegFromChannelTable[] = {
28    R600::sub0, R600::sub1, R600::sub2, R600::sub3,
29    R600::sub4, R600::sub5, R600::sub6, R600::sub7,
30    R600::sub8, R600::sub9, R600::sub10, R600::sub11,
31    R600::sub12, R600::sub13, R600::sub14, R600::sub15
32  };
33
34  assert(Channel < array_lengthof(SubRegFromChannelTable));
35  return SubRegFromChannelTable[Channel];
36}
37
38BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
39  BitVector Reserved(getNumRegs());
40
41  const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
42  const R600InstrInfo *TII = ST.getInstrInfo();
43
44  reserveRegisterTuples(Reserved, R600::ZERO);
45  reserveRegisterTuples(Reserved, R600::HALF);
46  reserveRegisterTuples(Reserved, R600::ONE);
47  reserveRegisterTuples(Reserved, R600::ONE_INT);
48  reserveRegisterTuples(Reserved, R600::NEG_HALF);
49  reserveRegisterTuples(Reserved, R600::NEG_ONE);
50  reserveRegisterTuples(Reserved, R600::PV_X);
51  reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
52  reserveRegisterTuples(Reserved, R600::ALU_CONST);
53  reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
54  reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
55  reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
56  reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
57  reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
58
59  for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
60                        E = R600::R600_AddrRegClass.end(); I != E; ++I) {
61    reserveRegisterTuples(Reserved, *I);
62  }
63
64  TII->reserveIndirectRegisters(Reserved, MF, *this);
65
66  return Reserved;
67}
68
69// Dummy to not crash RegisterClassInfo.
70static const MCPhysReg CalleeSavedReg = R600::NoRegister;
71
72const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
73  const MachineFunction *) const {
74  return &CalleeSavedReg;
75}
76
77Register R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
78  return R600::NoRegister;
79}
80
81unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
82  return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
83}
84
85unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
86  return GET_REG_INDEX(getEncodingValue(Reg));
87}
88
89const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
90                                                                   MVT VT) const {
91  switch(VT.SimpleTy) {
92  default:
93  case MVT::i32: return &R600::R600_TReg32RegClass;
94  }
95}
96
97bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
98  assert(!Register::isVirtualRegister(Reg));
99
100  switch (Reg) {
101  case R600::OQAP:
102  case R600::OQBP:
103  case R600::AR_X:
104    return false;
105  default:
106    return true;
107  }
108}
109
110void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
111                                           int SPAdj,
112                                           unsigned FIOperandNum,
113                                           RegScavenger *RS) const {
114  llvm_unreachable("Subroutines not supported yet");
115}
116
117void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
118  MCRegAliasIterator R(Reg, this, true);
119
120  for (; R.isValid(); ++R)
121    Reserved.set(*R);
122}
123