/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineSSAUpdater.cpp | 45 : InsertedPHIs(NewPHI), TII(MF.getSubtarget().getInstrInfo()), 120 const TargetInstrInfo *TII) { 122 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR); 154 VRC, MRI, TII); 190 Loc, VRC, MRI, TII); 297 Updater->TII); 308 Updater->TII); 116 InsertNewDef(unsigned Opcode, MachineBasicBlock *BB, MachineBasicBlock::iterator I, const TargetRegisterClass *RC, MachineRegisterInfo *MRI, const TargetInstrInfo *TII) argument
|
H A D | EarlyIfConversion.cpp | 83 const TargetInstrInfo *TII; member in class:__anon3455::SSAIfConv 169 TII = MF.getSubtarget().getInstrInfo(); 326 if (!TII->isPredicable(*I) || TII->isPredicated(*I)) { 341 TII->reverseBranchCondition(Condition); 348 TII->PredicateInstruction(*I, Condition); 482 if (TII->analyzeBranch(*Head, TBB, FBB, Cond)) { 523 if (!TII->canInsertSelect(*Head, Cond, PI.PHI->getOperand(0).getReg(), 572 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); 600 TII 703 const TargetInstrInfo *TII; member in class:__anon3456::EarlyIfConverter 940 const TargetInstrInfo *TII; member in class:__anon3458::EarlyIfPredicator [all...] |
H A D | MachineCombiner.cpp | 66 const TargetInstrInfo *TII; member in class:__anon3504::MachineCombiner 372 unsigned Idx = TII->get(Opc).getSchedClass(); 412 ResLenBeforeCombine + TII->getExtendResourceLenLimit() 418 ResLenBeforeCombine + TII->getExtendResourceLenLimit(); 483 TII->genAlternativeCodeSequence(Root, P, InsInstrs, DelInstrs, 555 if (!TII->getMachineCombinerPatterns(MI, Patterns)) 565 TII->genAlternativeCodeSequence(MI, P, InsInstrs, DelInstrs, 580 /*SkipDebugLoc*/false, /*AddNewLine*/true, TII); 584 /*SkipDebugLoc*/false, /*AddNewLine*/true, TII); 588 if (ML && TII [all...] |
H A D | ProcessImplicitDefs.cpp | 29 const TargetInstrInfo *TII; member in class:__anon3545::ProcessImplicitDefs 88 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 140 TII = MF.getSubtarget().getInstrInfo();
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 134 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); 138 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); 179 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY), 209 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); 282 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); 319 OpRC = TII->getRegClass(*II, IIOpNum, TRI, *MF); 329 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 384 II ? TRI->getAllocatableClass(TII->getRegClass(*II, IIOpNum, TRI, *MF)) 396 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); 464 BuildMI(*MBB, InsertPos, DL, TII [all...] |
H A D | ScheduleDAGSDNodes.cpp | 113 const TargetInstrInfo *TII, 127 const MCInstrDesc &II = TII->get(Def->getMachineOpcode()); 213 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); 245 if (!TII->areLoadsFromSameBasePtr(Base, User, Offset1, Offset2) || 278 if (!TII->shouldScheduleLoadsNear(BaseLoad, Load, BaseOff, Offset,NumLoads)) 319 const MCInstrDesc &MCID = TII->get(Opc); 377 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 395 if (N->isMachineOpcode() && TII->get(N->getMachineOpcode()).isCall()) 453 const MCInstrDesc &MCID = TII->get(Opc); 467 TII 111 CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, const TargetRegisterInfo *TRI, const TargetInstrInfo *TII, unsigned &PhysReg, int &Cost) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyCFGStackify.cpp | 214 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 339 TII.get(WebAssembly::BLOCK)) 371 TII.get(WebAssembly::END_BLOCK)); 385 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 418 TII.get(WebAssembly::LOOP)) 438 BuildMI(*AfterLoop, InsertPos, EndDL, TII.get(WebAssembly::END_LOOP)); 452 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 587 TII.get(WebAssembly::TRY)) 628 TII.get(WebAssembly::END_TRY)); 650 const auto &TII local 755 unstackifyVRegsUsedInSplitBB(MachineBasicBlock &MBB, MachineBasicBlock &Split, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo &TII) argument 813 const auto &TII = *MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local [all...] |
H A D | WebAssemblyRegisterInfo.cpp | 116 const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo(); local 125 TII->get(WebAssemblyFrameLowering::getOpcConst(MF)), 130 TII->get(WebAssemblyFrameLowering::getOpcAdd(MF)),
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 113 const TargetInstrInfo &TII; member in class:__anon4015::final 128 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), 304 const MCInstrDesc &II = TII.get(MachineInstOpcode); 316 TII.get(TargetOpcode::COPY), ResultReg) 327 const MCInstrDesc &II = TII.get(MachineInstOpcode); 344 TII.get(TargetOpcode::COPY), ResultReg) 355 const MCInstrDesc &II = TII.get(MachineInstOpcode); 370 TII.get(TargetOpcode::COPY), ResultReg) 380 const MCInstrDesc &II = TII.get(MachineInstOpcode); 389 TII [all...] |
H A D | Thumb2InstrInfo.cpp | 235 const ARMBaseInstrInfo &TII, 238 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) 255 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) 261 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg) 270 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg) 282 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg) 298 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) 313 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 348 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) 475 const ARMBaseInstrInfo &TII, 230 emitT2RegPlusImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, ARMCC::CondCodes Pred, Register PredReg, const ARMBaseInstrInfo &TII, unsigned MIFlags) argument [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
H A D | AArch64InstructionSelector.cpp | 337 const AArch64InstrInfo &TII; member in class:__anon3885::AArch64InstructionSelector 368 : InstructionSelector(), TM(TM), STI(STI), TII(*STI.getInstrInfo()), 725 getRegClassesForCopy(MachineInstr &I, const TargetInstrInfo &TII, argument 750 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII, argument 761 std::tie(SrcRC, DstRC) = getRegClassesForCopy(I, TII, MRI, TRI, RBI); 831 TII.get(AArch64::SUBREG_TO_REG), PromoteReg) 851 LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode()) 855 I.setDesc(TII.get(AArch64::COPY)); 1209 constrainSelectedInstRegOperands(*TestBitMI, TII, TRI, RBI); 1353 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 260 auto *TII = local 281 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset); 297 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset); 310 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset); 316 unsigned LAOpcode = TII->getOpcodeForOffset(SystemZ::LA, HighOffset); 318 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg) 323 TII->loadImmediate(MBB, MI, ScratchReg, HighOffset); 324 BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg) 333 MI->setDesc(TII->get(OpcodeForOffset));
|
H A D | SystemZElimCompare.cpp | 101 const SystemZInstrInfo *TII = nullptr; member in class:__anon4323::SystemZElimCompare 229 Branch->setDesc(TII->get(BRCT)); 247 unsigned LATOpcode = TII->getLoadAndTrap(MI.getOpcode()); 272 Branch->setDesc(TII->get(LATOpcode)); 289 unsigned Opcode = TII->getLoadAndTest(MI.getOpcode()); 294 auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode)); 332 MI.setDesc(TII->get(ConvOpc)); 367 const MCInstrDesc &Desc = TII->get(Opcode); 622 TII->getFusedCompare(Compare.getOpcode(), Type, &Compare); 667 Branch->setDesc(TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | Mips16ISelDAGToDAG.cpp | 73 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); local 83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) 85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) 88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); 89 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
|
H A D | MipsSERegisterInfo.cpp | 226 const MipsSEInstrInfo &TII = local 229 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg) 242 const MipsSEInstrInfo &TII = local 245 unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, 247 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
|
H A D | MipsConstantIslandPass.cpp | 342 const Mips16InstrInfo *TII; member in class:__anon4217::MipsConstantIslands 445 TII = (const Mips16InstrInfo *)STI->getInstrInfo(); 567 BuildMI(*BB, InsAt, DebugLoc(), TII->get(Mips::CONSTPOOL_ENTRY)) 794 BBI.Size += TII->getInstSizeInBytes(MI); 811 Offset += TII->getInstSizeInBytes(*I); 865 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB); 1108 UserMI->setDesc(TII->get(U.getLongFormOpcode())); 1238 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB); 1281 for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI); 1283 Offset += TII [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | R600ControlFlowFinalizer.cpp | 234 const R600InstrInfo *TII = nullptr; member in class:__anon3958::R600ControlFlowFinalizer 292 return TII->get(Opcode); 336 bool IsTex = TII->usesTextureCache(*ClauseHead); 343 if ((IsTex && !TII->usesTextureCache(*I)) || 344 (!IsTex && !TII->usesVertexCache(*I))) 366 TII->getSrcs(MI); 378 TII->getOperandIdx(MI.getOpcode(), R600::OpName::literal)); 401 TII->get(R600::LITERALS)) 419 if (!I->isBundle() && !TII->isALUInstr(I->getOpcode())) 443 TII [all...] |
H A D | R600ISelLowering.cpp | 297 const R600InstrInfo *TII = Subtarget->getInstrInfo(); local 303 if (TII->isLDSRetInstr(MI.getOpcode())) { 304 int DstIdx = TII->getOperandIdx(MI.getOpcode(), R600::OpName::dst); 314 TII->get(R600::getLDSNoRetOp(MI.getOpcode()))); 324 MachineInstr *NewMI = TII->buildDefaultInstruction( 327 TII->addFlag(*NewMI, 0, MO_FLAG_ABS); 332 MachineInstr *NewMI = TII->buildDefaultInstruction( 335 TII->addFlag(*NewMI, 0, MO_FLAG_NEG); 343 TII->addFlag(*defInstr, 0, MO_FLAG_MASK); 348 TII 2079 const R600InstrInfo *TII = Subtarget->getInstrInfo(); local 2209 const R600InstrInfo *TII = Subtarget->getInstrInfo(); local [all...] |
H A D | SILowerI1Copies.cpp | 60 const SIInstrInfo *TII = nullptr; member in class:__anon3982::SILowerI1Copies 105 return TII->getRegisterInfo().isSGPRReg(*MRI, Reg) && 106 TII->getRegisterInfo().getRegSizeInBits(Reg, *MRI) == 438 const SIInstrInfo *TII = ST.getInstrInfo(); 440 BuildMI(MBB, MBB.getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF), 466 TII = ST->getInstrInfo(); 527 assert(isVRegCompatibleReg(TII->getRegisterInfo(), *MRI, DstReg)); 531 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg) 708 assert(TII->getRegisterInfo().getRegSizeInBits(SrcReg, *MRI) == 32); 710 BuildMI(MBB, MI, DL, TII [all...] |
H A D | SIPreAllocateWWMRegs.cpp | 38 const SIInstrInfo *TII; member in class:__anon3991::SIPreAllocateWWMRegs 169 TII = ST.getInstrInfo(); 170 TRI = &TII->getRegisterInfo();
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVFrameLowering.cpp | 169 const RISCVInstrInfo *TII = STI.getInstrInfo(); local 175 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg) 188 TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag); 189 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) 218 const RISCVInstrInfo *TII = STI.getInstrInfo(); local 290 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 318 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 335 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 353 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) 364 const RISCVInstrInfo *TII local 662 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); local 698 const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64StackTaggingPreRA.cpp | 61 const AArch64InstrInfo *TII; member in class:__anon3876::AArch64StackTaggingPreRA 179 unsigned OpIdx = TII->getLoadStoreImmIdx(UseI->getOpcode()) - 1; 204 TII = static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo());
|
H A D | AArch64CondBrTuning.cpp | 48 const AArch64InstrInfo *TII; member in class:__anon3841::AArch64CondBrTuning 100 unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit); 106 TII->get(NewOpc), NewDestReg); 115 MachineBasicBlock *TargetMBB = TII->getBranchDestBlock(MI); 137 return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc)) 291 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
|
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/ |
H A D | VEInstrInfo.cpp | 495 const VEInstrInfo &TII = *STI.getInstrInfo(); local 531 BuildMI(BB, dl, TII.get(VE::BRCFLrr_t)) 542 BuildMI(BB, dl, TII.get(VE::LDrii), VE::SX61) 546 BuildMI(BB, dl, TII.get(VE::ORri), VE::SX62) 549 BuildMI(BB, dl, TII.get(VE::LEAzii), VE::SX63) 553 BuildMI(BB, dl, TII.get(VE::SHMLri)) 557 BuildMI(BB, dl, TII.get(VE::SHMLri)) 561 BuildMI(BB, dl, TII.get(VE::SHMLri)) 565 BuildMI(BB, dl, TII.get(VE::MONC)); 567 BuildMI(BB, dl, TII 579 const VEInstrInfo &TII = *STI.getInstrInfo(); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86CondBrFolding.cpp | 103 X86CondBrFolding(const X86InstrInfo *TII, argument 106 : TII(TII), MBPI(MBPI), MF(MF) {} 110 const X86InstrInfo *TII; member in class:__anon4422::X86CondBrFolding 225 BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI), TII->get(X86::JCC_1)) 231 BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1)) 252 TII->get(X86::JCC_1)) 258 BuildMI(*MBB, UncondBrI, MBB->findDebugLoc(UncondBrI), TII->get(X86::JMP_1)) 321 TII->get(X86::JCC_1)) 326 TII [all...] |