Searched refs:SELECT (Results 26 - 50 of 65) sorted by relevance

123

/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp104 setOperationAction(ISD::SELECT, XLenVT, Custom);
189 setOperationAction(ISD::SELECT, MVT::f32, Custom);
206 setOperationAction(ISD::SELECT, MVT::f64, Custom);
438 case ISD::SELECT:
809 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero);
810 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
861 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse);
862 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp494 setOperationAction(ISD::SELECT, MVT::i1, Custom);
1993 SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2053 SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
2106 RoundedA = DAG.getNode(ISD::SELECT, SL, VT, IsLarge, A, RoundedA);
2112 return DAG.getNode(ISD::SELECT, SL, VT, IsSmall, RoundedAForSmallA, RoundedA);
2137 RoundedA = DAG.getNode(ISD::SELECT, SL, VT, IsSmall,
2149 return DAG.getNode(ISD::SELECT, SL, VT, IsLarge, A, RoundedA);
2182 case ISD::SELECT:
2201 SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp89 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1353 case ISD::SELECT: {
1438 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, CCOp, TrueVal, FalseVal);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp352 setOperationAction(ISD::SELECT, MVT::f32, Custom);
353 setOperationAction(ISD::SELECT, MVT::f64, Custom);
354 setOperationAction(ISD::SELECT, MVT::i32, Custom);
373 setOperationAction(ISD::SELECT, MVT::i64, Custom);
501 setTargetDAGCombine(ISD::SELECT);
697 // of ISD::SELECT (obviously also inverting the condition) so that we can
716 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
1165 case ISD::SELECT:
1229 case ISD::SELECT: return lowerSELECT(Op, DAG);
2601 Lo = DAG.getNode(ISD::SELECT, D
[all...]
H A DMipsSEISelLowering.cpp131 setOperationAction(ISD::SELECT, MVT::f16, Promote);
248 setOperationAction(ISD::SELECT, MVT::i32, Legal);
252 setOperationAction(ISD::SELECT, MVT::f32, Legal);
257 setOperationAction(ISD::SELECT, MVT::f64, Custom);
295 setOperationAction(ISD::SELECT, MVT::i64, Legal);
468 case ISD::SELECT: return lowerSELECT(Op, DAG);
/freebsd-13-stable/sys/dev/usb/input/
H A Duhid_snes.c66 #define SELECT 0x10 macro
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp404 setOperationAction(ISD::SELECT, MVT::i32, Expand);
405 setOperationAction(ISD::SELECT, MVT::i64, Expand);
406 setOperationAction(ISD::SELECT, MVT::f32, Expand);
407 setOperationAction(ISD::SELECT, MVT::f64, Expand);
686 setOperationAction(ISD::SELECT, VT, Promote);
687 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
767 setOperationAction(ISD::SELECT, MVT::v4i32,
1034 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1100 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
1148 setOperationAction(ISD::SELECT, MV
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp233 setOperationAction(ISD::SELECT, MVT::i1, Promote);
234 setOperationAction(ISD::SELECT, MVT::i64, Custom);
235 setOperationAction(ISD::SELECT, MVT::f64, Promote);
236 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
744 setOperationAction(ISD::SELECT, MVT::v4i16, Custom);
745 setOperationAction(ISD::SELECT, MVT::v4f16, Custom);
752 setOperationAction(ISD::SELECT, MVT::v2i16, Promote);
753 AddPromotedToType(ISD::SELECT, MVT::v2i16, MVT::i32);
754 setOperationAction(ISD::SELECT, MVT::v2f16, Promote);
755 AddPromotedToType(ISD::SELECT, MV
[all...]
H A DR600ISelLowering.cpp171 setOperationAction(ISD::SELECT, MVT::i32, Expand);
172 setOperationAction(ISD::SELECT, MVT::f32, Expand);
173 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
174 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp998 if (Op.getOpcode() != ISD::SELECT)
1009 if (SOp.getOpcode() == ISD::SELECT && SOp.getNode()->hasOneUse()) {
1016 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, NewOr, VOp);
1020 SDValue NewSel = DAG.getNode(ISD::SELECT, DLS, VT, SC, VOp, NewOr);
1208 // We're generating a SELECT way after legalization, so keep the types
1212 SDValue Sel = DAG.getNode(ISD::SELECT, dl, SVT, OpI1,
H A DHexagonISelLoweringHVX.cpp953 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo);
959 IdxV = DAG.getNode(ISD::SELECT, dl, MVT::i32, PickHi, S, IdxV);
960 SingleV = DAG.getNode(ISD::SELECT, dl, SingleTy, PickHi, V1, V0);
1000 return DAG.getNode(ISD::SELECT, dl, VecTy, PickHi, InHi, InLo);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp397 case ISD::SELECT:
741 case ISD::SELECT:
H A DSelectionDAGDumper.cpp281 case ISD::SELECT: return "select";
H A DLegalizeFloatTypes.cpp128 case ISD::SELECT: R = SoftenFloatRes_SELECT(N); break;
1136 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2187 case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;
2387 // Construct a new SELECT node with the promoted true- and false- values.
2392 return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),
2527 case ISD::SELECT: R = SoftPromoteHalfRes_SELECT(N); break;
H A DDAGCombiner.cpp533 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
1631 case ISD::SELECT: return visitSELECT(N);
2014 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
2019 if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
7622 BinOpLHSVal.getOpcode() == ISD::SELECT;
8973 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags);
8975 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0,
8985 SDValue InnerSelect = DAG.getNode(ISD::SELECT, DL, N1.getValueType(),
8988 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1,
8996 if (N1->getOpcode() == ISD::SELECT
[all...]
H A DLegalizeIntegerTypes.cpp75 case ISD::SELECT: Res = PromoteIntRes_SELECT(N); break;
1368 case ISD::SELECT: Res = PromoteIntOp_SELECT(N, OpNo); break;
1627 EVT OpVT = N->getOpcode() == ISD::SELECT ? OpTy.getScalarType() : OpTy;
1908 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
4001 // NOTE: on targets without efficient SELECT of bools, we can always use
H A DLegalizeVectorTypes.cpp62 case ISD::SELECT: R = ScalarizeVecRes_SELECT(N); break;
702 /// <1 x i1>, so just convert to a normal ISD::SELECT
708 return DAG.getNode(ISD::SELECT, SDLoc(N), VT, ScalarCond, N->getOperand(1),
828 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break;
2745 case ISD::SELECT: Res = WidenVecRes_SELECT(N); break;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp102 setOperationAction(ISD::SELECT, VT, Expand);
688 // To "insert" a SELECT instruction, we actually have to insert the diamond
/freebsd-13-stable/tests/sys/fs/fusefs/
H A Dmockfs.cc897 case SELECT:
948 case SELECT:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1531 setOperationAction(ISD::SELECT, MVT::i32, Expand);
1532 setOperationAction(ISD::SELECT, MVT::f32, Expand);
1533 setOperationAction(ISD::SELECT, MVT::f64, Expand);
1534 setOperationAction(ISD::SELECT, MVT::f128, Expand);
1567 setOperationAction(ISD::SELECT, MVT::i64, Expand);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp268 setOperationAction(ISD::SELECT, MVT::i32, Custom);
269 setOperationAction(ISD::SELECT, MVT::i64, Custom);
270 setOperationAction(ISD::SELECT, MVT::f16, Custom);
271 setOperationAction(ISD::SELECT, MVT::f32, Custom);
272 setOperationAction(ISD::SELECT, MVT::f64, Custom);
318 setOperationAction(ISD::SELECT, MVT::f128, Custom);
479 setOperationAction(ISD::SELECT, MVT::f16, Promote);
518 setOperationAction(ISD::SELECT, MVT::v4f16, Expand);
545 setOperationAction(ISD::SELECT, MVT::v8f16, Expand);
714 setTargetDAGCombine(ISD::SELECT);
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp111 setOperationAction(ISD::SELECT, MVT::i8, Expand);
112 setOperationAction(ISD::SELECT, MVT::i16, Expand);
1591 // To "insert" a SELECT instruction, we insert the diamond
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp95 setOperationAction(ISD::SELECT, MVT::i8, Expand);
96 setOperationAction(ISD::SELECT, MVT::i16, Expand);
1570 // To "insert" a SELECT instruction, we actually have to insert the diamond
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DBasicTTIImpl.h869 if (ISD == ISD::SELECT) {
/freebsd-13-stable/sys/cam/scsi/
H A Dscsi_ses.h183 GEN_SES_CTRL_COMMON_ACCESSORS(select, SELECT)

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