/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
H A D | CorrelatedValuePropagation.cpp | 299 Value *Op0 = Cmp->getOperand(0); local 310 auto *I = dyn_cast<Instruction>(Op0); 315 LVI->getPredicateAt(Cmp->getPredicate(), Op0, C, Cmp); 815 Value *Op0 = C->getOperand(0); 820 LVI->getPredicateAt(C->getPredicate(), Op0, Op1, At);
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H A D | Reassociate.cpp | 2295 Value *Op0 = Ops[i].Op; 2297 if (std::less<Value *>()(Op1, Op0)) 2298 std::swap(Op0, Op1); 2299 auto it = PairMap[Idx].find({Op0, Op1}); 2318 auto Op0 = Ops[BestPair.first]; 2322 Ops.push_back(Op0); 2371 Value *Op0 = Ops[i]; 2373 if (std::less<Value *>()(Op1, Op0)) 2374 std::swap(Op0, Op1); 2375 if (!Visited.insert({Op0, Op [all...] |
H A D | CallSiteSplitting.cpp | 113 Value *Op0 = Cmp->getOperand(0); local 120 if (*I == Op0)
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMFastISel.cpp | 140 unsigned Op0, bool Op0IsKill); 143 unsigned Op0, bool Op0IsKill, 147 unsigned Op0, bool Op0IsKill, 302 unsigned Op0, bool Op0IsKill) { 308 Op0 = constrainOperandRegClass(II, Op0, 1); 311 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); 314 .addReg(Op0, Op0IsKill * RegState::Kill)); 324 unsigned Op0, bool Op0IsKill, 331 Op0 300 fastEmitInst_r(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) argument 322 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument 350 fastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument 1136 Value *Op0 = I->getOperand(0); local [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 2102 bool CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, 2188 MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, 2197 unsigned Opcode = Op0->getOpcode(); 2217 if (!Op0->hasOneMemOperand() || 2218 (*Op0->memoperands_begin())->isVolatile() || 2219 (*Op0->memoperands_begin())->isAtomic()) 2222 Align Alignment = (*Op0->memoperands_begin())->getAlign(); 2231 int OffImm = getMemoryOpOffset(*Op0); 2248 FirstReg = Op0->getOperand(0).getReg(); 2252 BaseReg = Op0 [all...] |
H A D | ARMISelLowering.cpp | 2342 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, local 2347 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i], 6411 SDValue Op0 = Op.getOperand(0); local 6420 CmpVT = Op0.getValueType().changeVectorElementTypeToInteger(); 6430 if (Op0.getValueType().isFloatingPoint() && !ST->hasMVEFloatOps()) 6436 if (Op0.getValueType().getVectorElementType() == MVT::i64 && 6442 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0); 6486 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0, 6488 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1, 6498 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0, 8611 SDValue Op0 = Op.getOperand(0); local 8920 SDValue Op0; local 9539 SDValue Op0 = Op->getOperand(0); local 11765 SDValue Op0; local 13402 SDValue Op0 = N->getOperand(0); local 13417 SDValue Op0 = N->getOperand(0); local 13673 SDValue Op0 = N->getOperand(0); local 13727 SDValue Op0 = N->getOperand(0); local 13761 SDValue Op0 = N->getOperand(0); local 14776 SDValue Op0 = N->getOperand(0); local 14811 SDValue Op0 = N->getOperand(0); local 14829 SDValue Op0 = N->getOperand(0); local 15429 SDValue Op0 = CMOV->getOperand(0); local 18660 Value *Op0 = SVI->getOperand(0); local [all...] |
H A D | MVEGatherScatterLowering.cpp | 260 Optional<int64_t> Op0 = getIfConst(I->getOperand(0)); local 262 if (!Op0 || !Op1) 265 return Optional<int64_t>{Op0.getValue() + Op1.getValue()}; 267 return Optional<int64_t>{Op0.getValue() * Op1.getValue()};
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 2064 GenericValue Op0 = getOperandValue(CE->getOperand(0), SF); local 2069 case Instruction::Add: Dest.IntVal = Op0.IntVal + Op1.IntVal; break; 2070 case Instruction::Sub: Dest.IntVal = Op0.IntVal - Op1.IntVal; break; 2071 case Instruction::Mul: Dest.IntVal = Op0.IntVal * Op1.IntVal; break; 2072 case Instruction::FAdd: executeFAddInst(Dest, Op0, Op1, Ty); break; 2073 case Instruction::FSub: executeFSubInst(Dest, Op0, Op1, Ty); break; 2074 case Instruction::FMul: executeFMulInst(Dest, Op0, Op1, Ty); break; 2075 case Instruction::FDiv: executeFDivInst(Dest, Op0, Op1, Ty); break; 2076 case Instruction::FRem: executeFRemInst(Dest, Op0, Op1, Ty); break; 2077 case Instruction::SDiv: Dest.IntVal = Op0 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/ |
H A D | BPFISelDAGToDAG.cpp | 162 SDValue Op0, Op1; local 167 if (!SelectAddr(Op, Op0, Op1)) 174 OutOps.push_back(Op0);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonGenPredicate.cpp | 414 MachineOperand &Op0 = MI->getOperand(0); local 415 assert(Op0.isDef()); 416 RegisterSubReg OutR(Op0);
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H A D | HexagonInstrInfo.cpp | 1254 const MachineOperand &Op0 = MI.getOperand(0); local 1258 Register Rd = Op0.getReg(); 1278 const MachineOperand &Op0 = MI.getOperand(0); local 1283 bool IsDestLive = !LiveOut.available(MRI, Op0.getReg()); 1288 if (Op0.getReg() != Op2.getReg()) { 1289 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill 1292 .add(Op0) 1296 T.addReg(Op0.getReg(), RegState::Implicit); 1299 if (Op0.getReg() != Op3.getReg()) { 1301 .add(Op0) 1311 MachineOperand &Op0 = MI.getOperand(0); local [all...] |
H A D | HexagonISelLowering.cpp | 2115 SDValue Op0 = Op.getOperand(0); local 2122 if (ty(Op0) != VecTy || ty(Op1) != VecTy) 2133 std::swap(Op0, Op1); 2169 return Op0; 2172 SDValue T0 = DAG.getBitcast(MVT::i32, Op0); 2179 typeJoin({ty(Op1), ty(Op0)}), {Op1, Op0}); 2186 typeJoin({ty(Op0), ty(Op1)}), {Op0, Op1}); 2196 return Op0; [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsFastISel.cpp | 231 unsigned Op0, bool Op0IsKill, 237 unsigned Op0, bool Op0IsKill, uint64_t imm1, 913 Value *Op0 = I->getOperand(0); local 926 SrcReg = getRegForValue(Op0); 1971 const Value *Op0 = I->getOperand(0); local 1972 unsigned Op0Reg = getRegForValue(Op0); 1982 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT(); 2125 unsigned Op0, bool Op0IsKill, 2136 Op0 = constrainOperandRegClass(II, Op0, I 236 fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t imm1, uint64_t imm2, unsigned Op3, bool Op3IsKill) argument 2123 fastEmitInst_rr(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) argument [all...] |
H A D | MipsInstrInfo.cpp | 879 const MachineOperand &Op0 = MI.getOperand(0); local 880 if (!Op0.isReg() || Reg != Op0.getReg())
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | IntrinsicLowering.cpp | 358 Value *Op0 = CI->getArgOperand(0); local 359 Type *IntPtr = DL.getIntPtrType(Op0->getType()); 363 Ops[0] = Op0;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelDAGToDAG.cpp | 127 SDValue Op0 = Node->getOperand(0); local 135 isConstantMask(Op0.getNode(), Mask)) { 141 CurDAG->SelectNodeTo(Node, RISCV::SRLIW, XLenVT, Op0.getOperand(0),
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CollectLOH.cpp | 557 const MachineOperand &Op0 = MI.getOperand(0); local 558 int Idx = mapRegToGPRIndex(Op0.getReg());
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H A D | AArch64ISelDAGToDAG.cpp | 616 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp, argument 619 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) { 620 std::swap(Op0, Op1); 621 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) 633 SDValue Op0 = N->getOperand(0); local 642 std::swap(Op0, Op1); 651 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal }; 1773 const SDNode *Op0 = N->getOperand(0).getNode(); local 1786 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND && 1787 isOpcWithIntImmediate(Op0 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | LoopInfo.cpp | 188 Value *Op0 = LatchCmpInst->getOperand(0); 190 if (Op0 == &IndVar || Op0 == &StepInst) 194 return Op0;
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H A D | IVDescriptors.cpp | 957 Value *Op0 = BinOp->getOperand(0); 960 if (L->isLoopInvariant(Op0)) 963 Def = Op0;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCISelDAGToDAG.cpp | 731 SDValue Op0 = N->getOperand(0); local 735 KnownBits LKnown = CurDAG->computeKnownBits(Op0); 742 unsigned Op0Opc = Op0.getOpcode(); 751 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 752 Op0.getOperand(0).getOpcode() == ISD::SRL) { 755 std::swap(Op0, Op1); 763 std::swap(Op0, Op1); 794 SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl), 4554 auto Op0 = Val.getOperand(0); local 4555 if (Op0 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeDAG.cpp | 1182 SDValue Op0 = Node->getOperand(0); 1185 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op1); 1192 NewNode = DAG.UpdateNodeOperands(Node, Op0, SAO); 1203 SDValue Op0 = Node->getOperand(0); 1207 SDValue SAO = DAG.getShiftAmountOperand(Op0.getValueType(), Op2); 1212 NewNode = DAG.UpdateNodeOperands(Node, Op0, Op1, SAO); 2270 SDValue Op0 = Node->getOperand(0); 2271 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 2272 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 2359 SDValue Op0 [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
H A D | IRTranslator.cpp | 283 Register Op0 = getOrCreateVReg(*U.getOperand(0)); local 292 MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags); 315 Register Op0 = getOrCreateVReg(*U.getOperand(0)); local 322 MIRBuilder.buildFNeg(Res, Op0, Flags); 329 Register Op0 = getOrCreateVReg(*U.getOperand(0)); local 336 MIRBuilder.buildICmp(Pred, Res, Op0, Op1); 345 MIRBuilder.buildFCmp(Pred, Res, Op0, Op1, 1051 Value &Op0 = *U.getOperand(0); local 1052 Register BaseReg = getOrCreateVReg(Op0); 1053 Type *PtrIRTy = Op0 1491 Register Op0 = getOrCreateVReg(*CI.getArgOperand(0)); local [all...] |
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/Analysis/ |
H A D | ScalarEvolution.h | 527 const SCEV *getAddExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 530 SmallVector<const SCEV *, 3> Ops = {Op0, Op1, Op2}; 542 const SCEV *getMulExpr(const SCEV *Op0, const SCEV *Op1, const SCEV *Op2, argument 545 SmallVector<const SCEV *, 3> Ops = {Op0, Op1, Op2};
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/AsmParser/ |
H A D | WebAssemblyAsmParser.cpp | 847 auto &Op0 = Inst.getOperand(0); variable 848 if (Op0.getImm() == -1) 849 Op0.setImm(Align);
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