Lines Matching refs:Op0
2342 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2347 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i],
6411 SDValue Op0 = Op.getOperand(0);
6420 CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
6430 if (Op0.getValueType().isFloatingPoint() && !ST->hasMVEFloatOps())
6436 if (Op0.getValueType().getVectorElementType() == MVT::i64 &&
6442 SDValue CastOp0 = DAG.getNode(ISD::BITCAST, dl, SplitVT, Op0);
6486 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0,
6488 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1,
6498 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0,
6500 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1,
6533 AndOp = Op0;
6534 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
6542 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
6544 SDValue Result = DAG.getNode(ARMISD::VTST, dl, CmpVT, Op0, Op1);
6553 std::swap(Op0, Op1);
6559 SingleOp = Op0;
6560 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
6573 Result = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1,
7297 SDValue Op0 = BV.getOperand(0).getOperand(0).getOperand(0);
7299 if (Op0.getValueType() != MVT::v4f32 || Op1.getValueType() != MVT::v4f32)
7310 if (!Check(BV.getOperand(i * 2 + 0), Op0, i))
7316 SDValue N1 = DAG.getNode(ARMISD::VCVTN, dl, VT, DAG.getUNDEF(VT), Op0,
7345 SDValue Op0 = BV.getOperand(0).getOperand(0).getOperand(0);
7347 if (Op0.getValueType() != MVT::v8f16 || (Offset != 0 && Offset != 1))
7358 if (!Check(BV.getOperand(i), Op0, 2 * i + Offset))
7362 return DAG.getNode(ARMISD::VCVTL, dl, VT, Op0,
8611 SDValue Op0 = Op.getOperand(0);
8613 if (!Op0.isUndef())
8615 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
8920 SDValue Op0;
8923 Op0 = SkipExtensionForVMULL(N0, DAG);
8924 assert(Op0.getValueType().is64BitVector() &&
8927 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
9539 SDValue Op0 = Op->getOperand(0);
9540 EVT VT = Op0.getValueType();
9553 SDValue Rev = DAG.getNode(RevOpcode, dl, VT, Op0);
9554 Op0 = DAG.getNode(BaseOpcode, dl, VT, Op0, Rev);
9561 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
9563 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
9565 SDValue Ext2 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
9567 SDValue Ext3 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
9573 SDValue Ext0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
9575 SDValue Ext1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, Op0,
11765 SDValue Op0;
11770 Op0 = Mul.getOperand(0);
11774 Op0 = Mul.getOperand(0);
11778 Op0 = Mul.getOperand(0).getOperand(0);
11782 Op0 = Mul->getOperand(0).getOperand(0);
11786 if (!Op0 || !Op1)
11790 Op0, Op1, Lo, Hi);
12577 if (SDValue Op0 = IsSignExt(N0)) {
12579 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0);
12584 if (SDValue Op0 = IsZeroExt(N0)) {
12586 SDValue New0a = DAG.getNode(ARMISD::VECTOR_REG_CAST, dl, MVT::v4i32, Op0);
13402 SDValue Op0 = N->getOperand(0);
13404 if (Op0.getOpcode() == ISD::BITCAST)
13405 Op0 = Op0.getOperand(0);
13408 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
13409 Op0.getNode() == Op1.getNode() &&
13410 Op0.getResNo() == 0 && Op1.getResNo() == 1)
13412 N->getValueType(0), Op0.getOperand(0));
13417 SDValue Op0 = N->getOperand(0);
13420 if (Op0->getOpcode() == ARMISD::VMOVrh)
13421 return Op0->getOperand(0);
13429 if (Op0->getOpcode() == ISD::BITCAST) {
13430 SDValue Copy = Op0->getOperand(0);
13441 if (LoadSDNode *LN0 = dyn_cast<LoadSDNode>(Op0)) {
13448 DCI.DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), Load.getValue(1));
13456 if (TLI.SimplifyDemandedBits(Op0, DemandedMask, DCI))
13673 SDValue Op0 = N->getOperand(0);
13681 return DCI.DAG.getNode(ARMISD::VCMPZ, dl, VT, Op0,
13687 if (isZeroVector(Op0))
13691 if (Op0->getOpcode() == ARMISD::VDUP && Op1->getOpcode() != ARMISD::VDUP)
13692 return DCI.DAG.getNode(ARMISD::VCMP, dl, VT, Op1, Op0,
13727 SDValue Op0 = N->getOperand(0);
13732 if (Op0->getOpcode() == ARMISD::VDUP) {
13733 SDValue X = Op0->getOperand(0);
13761 SDValue Op0 = N->getOperand(0);
13763 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
13765 Op0.getNumOperands() != 2 ||
13768 SDValue Concat0Op1 = Op0.getOperand(1);
13781 Op0.getOperand(0), Op1.getOperand(0));
14776 SDValue Op0 = N->getOperand(0);
14786 Op0, Op1->getOperand(1), N->getOperand(2));
14789 // Qd (Op0) are demanded from a VMOVN, depending on whether we are inserting
14799 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, KnownUndef,
14811 SDValue Op0 = N->getOperand(0);
14821 if (TLI.SimplifyDemandedVectorElts(Op0, Op0DemandedElts, KnownUndef,
14829 SDValue Op0 = N->getOperand(0);
14837 SDValue Merge = DAG.getMergeValues({Op0, Op1}, DL);
14845 SDValue NewShift = DAG.getNode(NewOpcode, DL, N->getVTList(), Op0, Op1,
15429 SDValue Op0 = CMOV->getOperand(0);
15451 std::swap(Op0, Op1);
15464 if (Op0 != Y)
18660 Value *Op0 = SVI->getOperand(0);
18671 FixedVectorType::get(IntTy, cast<FixedVectorType>(Op0->getType()));
18672 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
18754 Op0, Op1, createSequentialMask(Mask[IdxI], LaneLen, 0)));
18771 Op0, Op1, createSequentialMask(StartMask, LaneLen, 0)));