Searched refs:MCOperand (Results 26 - 50 of 151) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiMCInstLower.h18 class MCOperand;
34 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430MCInstLower.h18 class MCOperand;
34 MCOperand LowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCV.h28 class MCOperand;
36 MCOperand &MCOp, const AsmPrinter &AP);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMCInstLower.h36 MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym) const;
37 MCOperand lowerTypeIndexOperand(SmallVector<wasm::ValType, 1> &&,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCInst.cpp20 void MCOperand::print(raw_ostream &OS) const {
21 OS << "<MCOperand ";
39 bool MCOperand::evaluateAsConstantImm(int64_t &Imm) const {
47 bool MCOperand::isBareSymbolRef() const {
57 LLVM_DUMP_METHOD void MCOperand::dump() const {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.h30 class MCOperand;
68 unsigned getMachineOpValue(MCInst const &MI, MCOperand const &MO,
74 unsigned getExprOpValue(const MCInst &MI, const MCOperand &MO,
79 const MCOperand &MO,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp152 const MCOperand &Op = MI->getOperand(OpNo);
165 const MCOperand &Op = MI->getOperand(OpNo);
179 const MCOperand &Op = MI->getOperand(OpNo);
191 const MCOperand &Op = MI->getOperand(OpNo);
203 const MCOperand &Op = MI->getOperand(OpNo);
214 const MCOperand &RegOp) {
227 const MCOperand &OffsetOp,
240 const MCOperand &RegOp = MI->getOperand(OpNo);
241 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
242 const MCOperand
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H A DLanaiMCCodeEmitter.cpp57 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
110 const MCInst &Inst, const MCOperand &MCOp, SmallVectorImpl<MCFixup> &Fixups,
137 const MCOperand AluOp = Inst.getOperand(3);
142 const MCOperand Op2 = Inst.getOperand(2);
189 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
190 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
191 const MCOperand AluOp = Inst.getOperand(OpNo + 2);
221 const MCOperand Op1 = Inst.getOperand(OpNo + 0);
222 const MCOperand Op2 = Inst.getOperand(OpNo + 1);
223 const MCOperand AluMCO
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp71 addOperand(MCInst &Inst, const MCOperand& Opnd) {
78 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
100 return addOperand(Inst, MCOperand::createImm(Imm));
112 return addOperand(Inst, MCOperand::createImm(Offset));
390 insertNamedMCOperand(MI, MCOperand::createImm(0),
431 MCOperand::createReg(MI.getOperand(Tied).getReg()),
448 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
457 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
470 insertNamedMCOperand(MI, MCOperand::createImm(0),
475 insertNamedMCOperand(MI, MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFInstPrinter.cpp54 const MCOperand &Op = MI->getOperand(OpNo);
67 const MCOperand &RegOp = MI->getOperand(OpNo);
68 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
88 const MCOperand &Op = MI->getOperand(OpNo);
99 const MCOperand &Op = MI->getOperand(OpNo);
H A DBPFMCCodeEmitter.cpp53 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
87 const MCOperand &MO,
138 const MCOperand &MO = MI.getOperand(1);
162 const MCOperand Op1 = MI.getOperand(1);
166 MCOperand Op2 = MI.getOperand(2);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp181 MCStreamer &OutStreamer, const MCOperand &Imm,
255 MCOperand &ImmOp = Inst.getOperand(i);
260 T.addOperand(MCOperand::createExpr(NewHE));
279 MCOperand Reg = Inst.getOperand(0);
280 MCOperand S16 = Inst.getOperand(1);
285 Inst.addOperand(MCOperand::createReg(Hexagon::R0));
293 Inst.addOperand(MCOperand::createExpr(Zero));
300 Inst.addOperand(MCOperand::createExpr(Zero));
307 Inst.addOperand(MCOperand::createExpr(Zero));
314 Inst.addOperand(MCOperand
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H A DHexagonMCInstLower.cpp41 static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
93 return MCOperand::createExpr(ME);
114 MCOperand MCO;
127 MCO = MCOperand::createReg(MO.getReg());
138 MCO = MCOperand::createExpr(Expr);
145 MCO = MCOperand::createExpr(Expr);
153 MCO = MCOperand::createExpr(Expr);
179 MCB.addOperand(MCOperand::createInst(MCI));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp127 Instr.addOperand(MCOperand::createImm(AluOp));
170 Inst.addOperand(MCOperand::createReg(Reg));
179 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
181 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Offset)));
191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
193 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
203 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register]));
205 Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Offset)));
223 MI.addOperand(MCOperand::createImm(Insn));
230 Inst.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp100 const MCOperand &Dst = MI->getOperand(0);
101 const MCOperand &MO1 = MI->getOperand(1);
102 const MCOperand &MO2 = MI->getOperand(2);
103 const MCOperand &MO3 = MI->getOperand(3);
123 const MCOperand &Dst = MI->getOperand(0);
124 const MCOperand &MO1 = MI->getOperand(1);
125 const MCOperand &MO2 = MI->getOperand(2);
267 MCOperand NewReg;
272 NewReg = MCOperand::createReg(MRI.getMatchingSuperReg(
313 const MCOperand
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H A DARMMCCodeEmitter.cpp86 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
317 const MCOperand &MO = MI.getOperand(Op);
336 const MCOperand &MO = MI.getOperand(Op);
552 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
584 llvm_unreachable("Unable to encode MCOperand!");
592 const MCOperand &MO = MI.getOperand(OpIdx);
593 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
622 const MCOperand &MO = MI.getOperand(OpIdx);
659 const MCOperand MO = MI.getOperand(OpIdx);
672 const MCOperand M
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/Disassembler/
H A DSystemZDisassembler.cpp88 Inst.addOperand(MCOperand::createReg(RegNo));
174 Inst.addOperand(MCOperand::createImm(Imm));
182 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
256 Inst.addOperand(MCOperand::createImm(Value));
296 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
297 Inst.addOperand(MCOperand::createImm(Disp));
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
317 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
318 Inst.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp62 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
201 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
215 const MCOperand &MO = MI.getOperand(OpIdx);
236 const MCOperand &MO = MI.getOperand(OpIdx);
263 const MCOperand &MO = MI.getOperand(OpIdx);
264 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
272 assert(MO.isExpr() && "Unable to encode MCOperand!");
298 const MCOperand &MO = MI.getOperand(OpIdx);
320 const MCOperand &MO = MI.getOperand(OpIdx);
349 const MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMCInstLower.cpp35 MCOperand MipsMCInstLower::LowerSymbolOperand(const MachineOperand &MO,
120 return MCOperand();
174 return MCOperand::createExpr(Expr);
177 MCOperand MipsMCInstLower::LowerOperand(const MachineOperand &MO,
186 return MCOperand::createReg(MO.getReg());
188 return MCOperand::createImm(MO.getImm() + offset);
201 return MCOperand();
204 MCOperand MipsMCInstLower::createSub(MachineBasicBlock *BB1,
211 return MCOperand::createExpr(MipsMCExpr::create(Kind, Sub, *Ctx));
244 OutMI.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZMCInstLower.cpp79 MCOperand SystemZMCInstLower::lowerOperand(const MachineOperand &MO) const {
82 return MCOperand::createReg(MO.getReg());
85 return MCOperand::createImm(MO.getImm());
89 return MCOperand::createExpr(getExpr(MO, Kind));
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp384 Inst.addOperand(MCOperand::createReg(getReg()));
389 Inst.addOperand(MCOperand::createExpr(getImm()));
398 Inst.addOperand(MCOperand::createExpr(Expr));
408 Inst.addOperand(MCOperand::createExpr(NewExpr));
540 for (MCOperand &I : MCI)
543 NewInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
620 MCB.addOperand(MCOperand::createImm(0));
653 MCB.addOperand(MCOperand::createInst(SubInst));
1234 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp428 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
433 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
438 Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
443 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
462 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
467 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
472 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
477 Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
482 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
487 Inst.addOperand(MCOperand
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMMCInstLower.cpp38 MCOperand ARMAsmPrinter::GetSymbolRef(const MachineOperand &MO,
68 return MCOperand::createExpr(Expr);
73 MCOperand &MCOp) {
81 MCOp = MCOperand::createReg(MO.getReg());
84 MCOp = MCOperand::createImm(MO.getImm());
87 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create(
113 MCOp = MCOperand::createFPImm(Val.convertToDouble());
156 MCOperand MCOp;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.h24 class MCOperand;
42 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MCInstLower.cpp79 MCOperand AArch64MCInstLower::lowerSymbolOperandDarwin(const MachineOperand &MO,
111 return MCOperand::createExpr(Expr);
114 MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
188 return MCOperand::createExpr(Expr);
191 MCOperand AArch64MCInstLower::lowerSymbolOperandCOFF(const MachineOperand &MO,
238 return MCOperand::createExpr(Expr);
241 MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
253 MCOperand &MCOp) const {
261 MCOp = MCOperand::createReg(MO.getReg());
267 MCOp = MCOperand
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