Lines Matching refs:MCOperand
71 addOperand(MCInst &Inst, const MCOperand& Opnd) {
78 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
100 return addOperand(Inst, MCOperand::createImm(Imm));
112 return addOperand(Inst, MCOperand::createImm(Offset));
390 insertNamedMCOperand(MI, MCOperand::createImm(0),
431 MCOperand::createReg(MI.getOperand(Tied).getReg()),
448 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
457 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
470 insertNamedMCOperand(MI, MCOperand::createImm(0),
475 insertNamedMCOperand(MI, MCOperand::createImm(0),
595 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
599 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
604 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
620 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
625 // return MCOperand::createError(V);
626 return MCOperand();
630 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
631 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
635 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
645 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
684 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
688 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
692 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
696 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
700 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
704 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
713 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
717 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
721 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
725 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
729 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
733 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
737 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
741 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
745 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
749 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
753 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
757 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
761 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
768 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
774 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
780 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
787 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
791 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
795 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
799 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
803 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
807 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
819 return MCOperand::createImm(Literal);
822 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
826 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
907 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
917 return MCOperand::createImm(getInlineImmVal32(Imm));
919 return MCOperand::createImm(getInlineImmVal64(Imm));
922 return MCOperand::createImm(getInlineImmVal16(Imm));
1007 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
1050 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1069 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1101 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1125 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1166 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1170 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1174 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1201 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1244 Inst.addOperand(MCOperand::createExpr(Add));