Searched refs:Def (Results 126 - 150 of 182) sorted by relevance

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/freebsd-13-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaLambda.cpp1637 NamedDecl *Def; local
1638 FieldType->isIncompleteType(&Def);
1639 if (Def && Def->isInvalidDecl()) {
H A DSemaType.cpp8160 auto *Def = Var->getDefinition(); local
8161 if (!Def) {
8166 Def = Var->getDefinition();
8173 if (Var->getPointOfInstantiation().isInvalid() && Def) {
8184 if (Def) {
8185 DRE->setDecl(Def);
8186 QualType T = Def->getType();
8439 NamedDecl *Def = nullptr; local
8441 bool Incomplete = (T->isIncompleteType(&Def) ||
8446 if (Def
[all...]
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTwoAddressInstructionPass.cpp230 MachineInstr *Def = getSingleDef(TmpReg, MBB, MRI); local
231 if (!Def || !Def->isCopy())
234 TmpReg = Def->getOperand(1).getReg();
H A DInlineSpiller.cpp931 /// Check if \p Def fully defines a VReg with an undefined value.
934 static bool isRealSpill(const MachineInstr &Def) { argument
935 if (!Def.isImplicitDef())
937 assert(Def.getNumOperands() == 1 &&
939 // We can say that the VReg defined by Def is undef, only if it is
940 // fully defined by Def. Otherwise, some of the lanes may not be
942 return Def.getOperand(0).getSubReg();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp113 MachineInstr *Def = MRI.getVRegDef(Reg); local
114 assert(Def && "Operand not defined");
115 switch (Def->getOpcode()) {
120 for (const MachineOperand &BuildVecMO : Def->uses())
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLoopUnroll.cpp118 if (auto Def = dyn_cast<Instruction>(U)) {
119 Loop *DefLoop = LI->getLoopFor(Def->getParent());
/freebsd-13-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DAsmMatcherEmitter.cpp781 const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
782 assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
783 const auto &I = SubtargetFeatures.find(Def);
1298 // Def will be NULL for non-user defined register classes.
1299 Record *Def = RC.getDef();
1300 if (!Def)
1311 Init *DiagnosticType = Def->getValueInit("DiagnosticType");
1315 Init *DiagnosticString = Def->getValueInit("DiagnosticString");
1324 RegisterClassClasses.insert(std::make_pair(Def, CI));
H A DGICombinerEmitter.cpp283 static bool isSpecificDef(const Init &N, StringRef Def) { argument
285 if (OpI->getDef()->getName() == Def)
H A DGlobalISelEmitter.cpp2911 for (auto Def : I->ImplicitDefs) {
2912 auto Namespace = Def->getValue("Namespace")
2913 ? Def->getValueAsString("Namespace")
2917 << MatchTable::NamedValue(Namespace, Def->getName())
3556 if (!P.Def || P.getCondString().empty())
3558 declareSubtargetFeature(P.Def);
3559 M.addRequiredFeature(P.Def);
4568 auto Def = DefaultDefOp->getDef();
4569 if (Def->getName() == "undef_tied_input") {
4581 DstMIBuilder.addRenderer<AddRegisterRenderer>(Def);
[all...]
H A DSubtargetEmitter.cpp163 Record *Def = DefList[i]; local
166 OS << " " << Def->getName() << " = " << i << ",\n";
169 FeatureMap[Def] = i;
H A DCodeGenRegisters.h640 const CodeGenSubRegIndex *findSubRegIdx(const Record* Def) const;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2SizeReduction.cpp262 static bool isHighLatencyCPSR(MachineInstr *Def) { argument
263 switch(Def->getOpcode()) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1919 MachineInstr *Def = LIS->getInstructionFromIndex(DefIdx); local
1921 if (!Def || !MDT.dominates(Def, &Use))
1924 assert(Def->modifiesRegister(Reg, this));
1926 return Def;
H A DAMDGPUSubtarget.h1246 void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
H A DAMDGPUMachineCFGStructurizer.cpp1047 MachineOperand *Def = &(*(MRI->def_begin(Reg)));
1049 bool UseIsOutsideDefMBB = Def->getParent()->getParent() != MBB;
2109 MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2110 if (Def->getParent()->getParent() == MBB) {
2122 MachineOperand *Def = &(*(MRI->def_begin(SourceReg)));
2123 if (Def->getParent()->getParent() != MBB) {
H A DAMDGPURegisterBankInfo.cpp752 for (MachineOperand &Def : MI.defs()) {
753 LLT ResTy = MRI.getType(Def.getReg());
754 const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI);
755 ResultRegs.push_back(Def.getReg());
1294 MachineInstr *Def = getDefIgnoringCopies(Reg, MRI); local
1295 if (!Def)
1299 return Def->getOperand(0).getReg();
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp1097 MachineInstr *Def = MRI.getVRegDef(CarryInReg);
1098 while (Def->getOpcode() == TargetOpcode::G_TRUNC) {
1099 CarryInReg = Def->getOperand(1).getReg();
1100 Def = MRI.getVRegDef(CarryInReg);
1104 if (Def->getOpcode() == TargetOpcode::G_UADDE) {
/freebsd-13-stable/contrib/llvm-project/clang/lib/AST/
H A DDeclPrinter.cpp1127 const FunctionDecl *Def; local
1128 if (PrevDecl->isDefined(Def) && Def != PrevDecl)
H A DRecordLayoutBuilder.cpp2122 const FunctionDecl *Def; local
2123 if (MD->hasBody(Def) && Def->isInlineSpecified())
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/TableGen/
H A DRecord.h1181 Record *Def; member in class:llvm::final::DefInit
1197 Record *getDef() const { return Def; }
1216 DefInit *Def = nullptr; // after instantiation member in class:llvm::final::final
/freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachinePipeliner.h599 bool isLoopCarriedDefOfUse(SwingSchedulerDAG *SSD, MachineInstr *Def,
/freebsd-13-stable/contrib/llvm-project/clang/include/clang/AST/
H A DDeclObjC.h1452 if (const ObjCInterfaceDecl *Def = getDefinition())
1453 return ivar_iterator(Def->decls_begin());
1460 if (const ObjCInterfaceDecl *Def = getDefinition())
1461 return ivar_iterator(Def->decls_end());
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopFuse.cpp1029 if (Instruction *Def = dyn_cast<Instruction>(Op))
1030 if (FC0.L->contains(Def->getParent())) {
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyCFGStackify.cpp764 if (MachineInstr *Def = MRI.getUniqueVRegDef(MO.getReg()))
765 if (Def->getParent() == &MBB)
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp587 SUnit *Def = &SUnits[N->getNodeId()]; local
588 CallSeqEndForStart[Def] = SU;
591 LiveRegDefs[CallResource] = Def;

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