| /freebsd-13-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 92 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
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| H A D | MachineOperand.h | 784 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/ |
| H A D | HexagonAsmParser.cpp | 433 CreateReg(MCContext &Context, unsigned RegNum, SMLoc S, SMLoc E) { function in struct:__anon4092::HexagonOperand
892 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
910 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
922 HexagonOperand::CreateReg(getContext(), Register, Begin, End));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 60 Info.Callee = MachineOperand::CreateReg(GetCalleeReg(), false);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 100 MI.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
255 return MachineOperand::CreateReg(DstReg, MO.isDef(), MO.isImplicit(),
302 I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
325 I.addOperand(MachineOperand::CreateReg(AMDGPU::SCC, true, // isDef
364 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
455 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
2311 I.addOperand(*MF, MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
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| H A D | R600InstrInfo.cpp | 717 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
737 Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false));
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| H A D | SIWholeQuadMode.cpp | 846 MI->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
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| H A D | AMDGPUMachineCFGStructurizer.cpp | 1882 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
2342 MachineOperand::CreateReg(Reg, false, false, true);
2400 MachineOperand RegOp = MachineOperand::CreateReg(Reg, false, false, true);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 905 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
916 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
973 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
987 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
2201 MachineOperand::CreateReg(*ImpDefs, true, true));
2207 MachineOperand::CreateReg(*ImpUses, false, true));
4568 Cond.push_back(MachineOperand::CreateReg(
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 1436 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1472 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1495 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1530 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1538 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
1579 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
1620 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
6029 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6031 MOs.push_back(MachineOperand::CreateReg(0, false));
6033 MOs.push_back(MachineOperand::CreateReg(
[all...] |
| H A D | X86FloatingPoint.cpp | 1111 MachineOperand::CreateReg(X86::ST0, /*isDef*/ true, /*isImp*/ true));
1157 MachineOperand::CreateReg(X86::ST0, /*isDef*/ false, /*isImp*/ true));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelDAGToDAG.cpp | 172 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
179 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
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| H A D | MipsInstrInfo.cpp | 861 return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/ |
| H A D | VEAsmParser.cpp | 578 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, function in class:__anon4344::VEOperand
1403 Op = VEOperand::CreateReg(RegNo, S, E);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/ |
| H A D | X86Operand.h | 624 CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc, function in struct:llvm::final
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 888 static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str, function in class:__anon4201::MipsOperand
1507 return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser);
1515 return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser);
1523 return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser);
1531 return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser);
1539 return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser);
1547 return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser);
1555 return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser);
1563 return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser);
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetInstrInfo.cpp | 1182 return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
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| H A D | ModuloSchedule.cpp | 1812 MI.addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/false));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 853 PN->addOperand(MachineOperand::CreateReg(MuxR, false, false, false, false,
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| H A D | HexagonFrameLowering.cpp | 541 RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
969 RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
2616 MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
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| H A D | HexagonSplitDouble.cpp | 621 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
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| H A D | HexagonConstExtenders.cpp | 253 return MachineOperand::CreateReg(Reg, /*Def*/false, /*Imp*/false,
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1191 MachineOperand::CreateReg(*ImpDefs, true, true));
1195 MachineOperand::CreateReg(*ImpUses, false, true));
1552 Dest = MachineOperand::CreateReg(
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 7855 DestBase = MachineOperand::CreateReg(NextDestReg, false);
7856 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
7875 DestBase = MachineOperand::CreateReg(Reg, false);
7884 SrcBase = MachineOperand::CreateReg(Reg, false);
8006 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
8015 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
8020 MI.addOperand(MachineOperand::CreateReg(Reg, true, true));
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| /freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 6877 return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
6882 return ParamLoadedValue(MachineOperand::CreateReg(SrcReg, false), Expr);
6888 return ParamLoadedValue(MachineOperand::CreateReg(SrcSubReg, false), Expr);
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