/freebsd-13-stable/contrib/byacc/test/btyacc/ |
H A D | btyacc_demo.tab.c | 136 enum Operator { ADD, SUB, MUL, MOD, DIV, DEREF }; enumerator in enum:Operator 2019 { yyval.expr = build_expr(yystack.l_mark[-3].expr, ADD, yystack.l_mark[0].expr); }
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H A D | quote_calc.tab.c | 170 #define ADD 258 macro 338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
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H A D | quote_calc2.tab.c | 170 #define ADD 258 macro 338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV", 350 "expr : expr \"ADD\" expr",
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/freebsd-13-stable/contrib/kyua/store/ |
H A D | migrate_v1_v2.sql | 117 ALTER TABLE test_cases ADD COLUMN metadata_id INTEGER;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 281 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 }, 282 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 }, 920 // Folded into a ADC/ADD/AND/BIC/CMP/EOR/MVN/ORR/ORN/RSB/SBC/SUB
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H A D | ARMFastISel.cpp | 851 Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, 1747 case ISD::ADD: 2844 return SelectBinaryIntOp(I, ISD::ADD);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 499 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) { 800 /// need to create a real ADD instruction from it anyway and there's no point in 802 /// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding 1020 if (N.getOpcode() != ISD::ADD) 1090 // Check if the given immediate is preferred by ADD. If an immediate can be 1091 // encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be 1094 // Constant in [0x0, 0xfff] can be encoded in ADD. 1097 // Check if it can be encoded in an "ADD LSL #12". 1099 // As a single MOVZ is faster than a "ADD o [all...] |
/freebsd-13-stable/lib/libc/resolv/ |
H A D | res_mkupdate.c | 185 case ADD:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAGDumper.cpp | 229 case ISD::ADD: return "add";
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H A D | SelectionDAG.cpp | 1962 VAList = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, 1971 Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList, 2313 case ISD::ADD: 3219 case ISD::ADD: 3833 case ISD::ADD: 3840 // Special case decrementing a value (ADD X, -1): 4110 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) || 4846 case ISD::ADD: return C1 + C2; 4897 case ISD::ADD: break; 5289 case ISD::ADD [all...] |
H A D | LegalizeVectorTypes.cpp | 111 case ISD::ADD: 909 case ISD::ADD: 990 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, BytesIncrement); 2120 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break; 2759 case ISD::ADD:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUTargetTransformInfo.cpp | 482 case ISD::ADD:
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H A D | R600ISelLowering.cpp | 176 // ADD, SUB overflow. 485 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); 1173 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); 1404 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); 1822 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVExpandAtomicPseudoInsts.cpp | 310 BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
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H A D | RISCVFrameLowering.cpp | 180 unsigned Opc = RISCV::ADD;
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 357 setOperationAction(ISD::ADD, VT, Legal); 1440 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, 1458 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue, 1592 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot, 1616 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, 3042 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result, 3179 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset); 3208 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset); 3379 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr, 3437 NeededSpace = DAG.getNode(ISD::ADD, D [all...] |
H A D | SystemZISelDAGToDAG.cpp | 462 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) { 1855 Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
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/freebsd-13-stable/sys/netipsec/ |
H A D | key_debug.c | 97 SADB_NAME(ADD);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCFastISel.cpp | 1292 case ISD::ADD: 1961 return SelectBinaryIntOp(I, ISD::ADD);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyISelLowering.cpp | 875 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode, 1236 return DAG.getNode(ISD::ADD, DL, VT, BaseAddr, SymAddr);
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86IntrinsicsInfo.h | 340 X86_INTRINSIC_DATA(addcarry_32, ADX, X86ISD::ADC, X86ISD::ADD), 341 X86_INTRINSIC_DATA(addcarry_64, ADX, X86ISD::ADC, X86ISD::ADD),
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H A D | X86ISelLowering.h | 391 ADD, 427 // ADD for masks.
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 501 setTargetDAGCombine(ISD::ADD); 1591 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx], 2570 DAG.getNode(ISD::ADD, dl, PtrVT, Arg, 4318 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with 4426 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD. 4740 case ISD::ADD:
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/freebsd-13-stable/contrib/llvm-project/llvm/lib/TableGen/ |
H A D | Record.cpp | 1013 case ADD: 1029 case ADD: Result = LHSv + RHSv; break; 1059 case ADD: Result = "!add"; break;
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H A D | TGParser.cpp | 1090 case tgtok::XADD: Code = BinOpInit::ADD; break; 1237 if (Code != BinOpInit::ADD && Code != BinOpInit::AND && 1275 Code == BinOpInit::CONCAT || Code == BinOpInit::ADD ||
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