Searched refs:ADD (Results 101 - 125 of 140) sorted by relevance

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/freebsd-13-stable/contrib/byacc/test/btyacc/
H A Dbtyacc_demo.tab.c136 enum Operator { ADD, SUB, MUL, MOD, DIV, DEREF }; enumerator in enum:Operator
2019 { yyval.expr = build_expr(yystack.l_mark[-3].expr, ADD, yystack.l_mark[0].expr); }
H A Dquote_calc.tab.c170 #define ADD 258 macro
338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
H A Dquote_calc2.tab.c170 #define ADD 258 macro
338 0,0,"error","OP_ADD","\"ADD\"","OP_SUB","\"SUB\"","OP_MUL","\"MUL\"","OP_DIV",
350 "expr : expr \"ADD\" expr",
/freebsd-13-stable/contrib/kyua/store/
H A Dmigrate_v1_v2.sql117 ALTER TABLE test_cases ADD COLUMN metadata_id INTEGER;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp281 { ISD::ADD, MVT::v4i32, MVT::v4i16, 0 },
282 { ISD::ADD, MVT::v8i16, MVT::v8i8, 0 },
920 // Folded into a ADC/ADD/AND/BIC/CMP/EOR/MVN/ORR/ORN/RSB/SBC/SUB
H A DARMFastISel.cpp851 Addr.Base.Reg = fastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
1747 case ISD::ADD:
2844 return SelectBinaryIntOp(I, ISD::ADD);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp499 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
800 /// need to create a real ADD instruction from it anyway and there's no point in
802 /// a single pseudo-instruction for an ADRP/ADD pair so over-aggressive folding
1020 if (N.getOpcode() != ISD::ADD)
1090 // Check if the given immediate is preferred by ADD. If an immediate can be
1091 // encoded in an ADD, or it can be encoded in an "ADD LSL #12" and can not be
1094 // Constant in [0x0, 0xfff] can be encoded in ADD.
1097 // Check if it can be encoded in an "ADD LSL #12".
1099 // As a single MOVZ is faster than a "ADD o
[all...]
/freebsd-13-stable/lib/libc/resolv/
H A Dres_mkupdate.c185 case ADD:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp229 case ISD::ADD: return "add";
H A DSelectionDAG.cpp1962 VAList = getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
1971 Tmp1 = getNode(ISD::ADD, dl, VAList.getValueType(), VAList,
2313 case ISD::ADD:
3219 case ISD::ADD:
3833 case ISD::ADD:
3840 // Special case decrementing a value (ADD X, -1):
4110 if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
4846 case ISD::ADD: return C1 + C2;
4897 case ISD::ADD: break;
5289 case ISD::ADD
[all...]
H A DLegalizeVectorTypes.cpp111 case ISD::ADD:
909 case ISD::ADD:
990 Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, BytesIncrement);
2120 case ISD::VECREDUCE_ADD: CombineOpc = ISD::ADD; break;
2759 case ISD::ADD:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUTargetTransformInfo.cpp482 case ISD::ADD:
H A DR600ISelLowering.cpp176 // ADD, SUB overflow.
485 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY);
1173 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1404 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset);
1822 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp310 BuildMI(LoopMBB, DL, TII->get(RISCV::ADD), ScratchReg)
H A DRISCVFrameLowering.cpp180 unsigned Opc = RISCV::ADD;
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp357 setOperationAction(ISD::ADD, VT, Legal);
1440 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
1458 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, ArgValue,
1592 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, SpillSlot,
1616 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
3042 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
3179 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
3208 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
3379 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
3437 NeededSpace = DAG.getNode(ISD::ADD, D
[all...]
H A DSystemZISelDAGToDAG.cpp462 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
1855 Result = CurDAG->getNode(ISD::ADD, DL, MVT::i32, Result,
/freebsd-13-stable/sys/netipsec/
H A Dkey_debug.c97 SADB_NAME(ADD);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp1292 case ISD::ADD:
1961 return SelectBinaryIntOp(I, ISD::ADD);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp875 SDValue Add = DAG.getNode(ISD::ADD, DL, PtrVT, FINode,
1236 return DAG.getNode(ISD::ADD, DL, VT, BaseAddr, SymAddr);
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h340 X86_INTRINSIC_DATA(addcarry_32, ADX, X86ISD::ADC, X86ISD::ADD),
341 X86_INTRINSIC_DATA(addcarry_64, ADX, X86ISD::ADC, X86ISD::ADD),
H A DX86ISelLowering.h391 ADD,
427 // ADD for masks.
/freebsd-13-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp501 setTargetDAGCombine(ISD::ADD);
1591 SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
2570 DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
4318 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4426 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4740 case ISD::ADD:
/freebsd-13-stable/contrib/llvm-project/llvm/lib/TableGen/
H A DRecord.cpp1013 case ADD:
1029 case ADD: Result = LHSv + RHSv; break;
1059 case ADD: Result = "!add"; break;
H A DTGParser.cpp1090 case tgtok::XADD: Code = BinOpInit::ADD; break;
1237 if (Code != BinOpInit::ADD && Code != BinOpInit::AND &&
1275 Code == BinOpInit::CONCAT || Code == BinOpInit::ADD ||

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