Searched refs:phy (Results 176 - 200 of 265) sorted by relevance

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/freebsd-12-stable/sys/dev/usb/net/
H A Dif_rue.c310 rue_miibus_readreg(device_t dev, int phy, int reg) argument
317 if (phy != 0) /* RTL8150 supports PHY == 0, only */
349 device_printf(sc->sc_ue.ue_dev, "bad phy register\n");
362 rue_miibus_writereg(device_t dev, int phy, int reg, int data) argument
368 if (phy != 0) /* RTL8150 supports PHY == 0, only */
399 device_printf(sc->sc_ue.ue_dev, " bad phy register\n");
H A Dif_smsc.c427 * @phy: the number of phy reading from
430 * Attempts to read a phy register over the MII bus.
440 smsc_miibus_readreg(device_t dev, int phy, int reg) argument
456 addr = (phy << 11) | (reg << 6) | SMSC_MII_READ | SMSC_MII_BUSY;
475 * @phy: the number of phy writing to
479 * Attempts to write a phy register over the MII bus.
488 smsc_miibus_writereg(device_t dev, int phy, int reg, int val) argument
494 if (sc->sc_phyno != phy)
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H A Dif_axe.c321 axe_miibus_readreg(device_t dev, int phy, int reg) argument
332 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
352 axe_miibus_writereg(device_t dev, int phy, int reg, int val) argument
363 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
/freebsd-12-stable/sys/dev/smc/
H A Dif_smc.c992 smc_miibus_readreg(device_t dev, int phy, int reg) argument
1003 val = mii_bitbang_readreg(dev, &smc_mii_bitbang_ops, phy, reg);
1010 smc_miibus_writereg(device_t dev, int phy, int reg, int data) argument
1020 mii_bitbang_writereg(dev, &smc_mii_bitbang_ops, phy, reg, data);
/freebsd-12-stable/sys/dev/ath/
H A Dif_ath_ioctl.c267 if (rt->info[sc->sc_txrix].phy & IEEE80211_T_HT)
/freebsd-12-stable/sys/arm/allwinner/
H A Dif_emac.c666 /* Start translate from fifo to phy. */
1012 emac_miibus_readreg(device_t dev, int phy, int reg) argument
1019 /* Issue phy address and reg */
1020 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1021 /* Pull up the phy io line */
1027 /* Push down the phy io line */
1036 emac_miibus_writereg(device_t dev, int phy, int reg, int data) argument
1042 /* Issue phy address and reg */
1043 EMAC_WRITE_REG(sc, EMAC_MAC_MADR, (phy << 8) | reg);
1046 /* Pull up the phy i
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H A Dif_awg.c232 awg_miibus_readreg(device_t dev, int phy, int reg) argument
242 (phy << PHY_ADDR_SHIFT) |
254 device_printf(dev, "phy read timeout, phy=%d reg=%d\n",
255 phy, reg);
261 awg_miibus_writereg(device_t dev, int phy, int reg, int val) argument
271 (phy << PHY_ADDR_SHIFT) |
281 device_printf(dev, "phy write timeout, phy=%d reg=%d\n",
282 phy, re
[all...]
/freebsd-12-stable/sys/dev/sis/
H A Dif_sis.c470 sis_miibus_readreg(device_t dev, int phy, int reg) argument
477 if (phy != 0)
503 if (phy != 0)
507 (phy << 11) | (reg << 6) | SIS_PHYOP_READ);
528 return (mii_bitbang_readreg(dev, &sis_mii_bitbang_ops, phy,
533 sis_miibus_writereg(device_t dev, int phy, int reg, int data) argument
540 if (phy != 0)
555 if (phy != 0)
558 CSR_WRITE_4(sc, SIS_PHYCTL, (data << 16) | (phy << 11) |
571 mii_bitbang_writereg(dev, &sis_mii_bitbang_ops, phy, re
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/freebsd-12-stable/sys/dev/ice/
H A Dice_common.c200 ice_debug(hw, ICE_DBG_LINK, "get phy caps - report_mode = 0x%x\n",
226 pi->phy.phy_type_low = LE64_TO_CPU(pcaps->phy_type_low);
227 pi->phy.phy_type_high = LE64_TO_CPU(pcaps->phy_type_high);
228 ice_memcpy(pi->phy.link_info.module_type, &pcaps->module_type,
229 sizeof(pi->phy.link_info.module_type),
297 hw_link_info = &pi->phy.link_info;
432 li_old = &pi->phy.link_info_old;
433 hw_media_type = &pi->phy.media_type;
434 li = &pi->phy.link_info;
500 pi->phy
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/freebsd-12-stable/sys/dev/ixl/
H A Di40e_common.c1011 hw->phy.get_link_info = TRUE;
1245 switch (hw->phy.link_info.phy_type) {
1743 hw->phy.phy_types = LE32_TO_CPU(abilities->phy_type);
1744 hw->phy.phy_types |=
1820 /* Get the current phy config */
1994 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
2013 i40e_memcpy(&hw->phy.link_info_old, hw_link_info,
2018 hw->phy.media_type = i40e_get_media_type(hw);
2062 hw->phy.phy_types = LE32_TO_CPU(tmp);
2063 hw->phy
[all...]
/freebsd-12-stable/sys/dev/dc/
H A Dif_dc.c662 dc_miibus_readreg(device_t dev, int phy, int reg) argument
670 if (phy == (MII_NPHY - 1)) {
695 (phy << 23) | (reg << 18));
709 ((phy << DC_ULI_PHY_ADDR_SHIFT) & DC_ULI_PHY_ADDR_MASK) |
720 device_printf(dev, "phy read timed out\n");
748 device_printf(dev, "phy_read: bad phy register %x\n",
763 rval = mii_bitbang_readreg(dev, &dc_mii_bitbang_ops, phy, reg);
771 dc_miibus_writereg(device_t dev, int phy, int reg, int data) argument
780 (phy << 23) | (reg << 10) | data);
790 ((phy << DC_ULI_PHY_ADDR_SHIF
2027 int error, mac_offset, n, phy, rid, tmp; local
[all...]
/freebsd-12-stable/sys/dev/nfe/
H A Dif_nfe.c938 uint32_t link, misc, phy, seed; local
943 phy = NFE_READ(sc, NFE_PHY_IFACE);
944 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T);
953 phy |= NFE_PHY_HDX; /* half-duplex */
961 phy |= NFE_PHY_1000T;
966 phy |= NFE_PHY_100TX;
974 if ((phy & 0x10000000) != 0) {
985 NFE_WRITE(sc, NFE_PHY_IFACE, phy);
1029 nfe_miibus_readreg(device_t dev, int phy, int reg) argument
1042 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIF
1070 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) argument
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/freebsd-12-stable/sys/dev/hme/
H A Dif_hme.c357 "MII device %s at phy %d, instance %d\n",
1423 hme_mii_readreg(device_t dev, int phy, int reg) argument
1432 if (phy == HME_PHYAD_EXTERNAL)
1442 (phy << HME_MIF_FO_PHYAD_SHIFT) |
1460 hme_mii_writereg(device_t dev, int phy, int reg, int val) argument
1469 if (phy == HME_PHYAD_EXTERNAL)
1479 (phy << HME_MIF_FO_PHYAD_SHIFT) |
/freebsd-12-stable/sys/dev/tl/
H A Dif_tl.c707 tl_miibus_readreg(dev, phy, reg)
709 int phy, reg;
724 val = mii_bitbang_readreg(dev, &tl_mii_bitbang_ops, phy, reg);
735 tl_miibus_writereg(dev, phy, reg, data)
737 int phy, reg, data;
752 mii_bitbang_writereg(dev, &tl_mii_bitbang_ops, phy, reg, data);
/freebsd-12-stable/sys/gnu/dev/bwn/phy_n/
H A Dif_bwn_phy_n_tables.c3742 struct bwn_phy *phy = &mac->mac_phy; local
3745 switch (phy->rev) {
3747 if (phy->rf_rev == 14)
3751 if (phy->rf_rev == 9)
3755 if (phy->rf_rev == 5)
3773 switch (phy->rev) {
3775 if (phy->rf_rev == 9)
3792 struct bwn_phy *phy = &mac->mac_phy; local
3807 switch (phy->rev) {
3832 switch (phy
3861 struct bwn_phy *phy = &mac->mac_phy; local
3897 struct bwn_phy *phy = &mac->mac_phy; local
[all...]
/freebsd-12-stable/sys/dev/vr/
H A Dif_vr.c244 vr_miibus_readreg(device_t dev, int phy, int reg) argument
261 device_printf(sc->vr_dev, "phy read timeout %d:%d\n", phy, reg);
267 vr_miibus_writereg(device_t dev, int phy, int reg, int data) argument
285 device_printf(sc->vr_dev, "phy write timeout %d:%d\n", phy,
601 int i, phy, pmc; local
771 phy = 1;
773 phy = CSR_READ_1(sc, VR_PHYADDR) & VR_PHYADDR_MASK;
775 vr_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_AN
[all...]
/freebsd-12-stable/sys/dev/xl/
H A Dif_xl.c417 xl_miibus_readreg(device_t dev, int phy, int reg) argument
426 return (mii_bitbang_readreg(dev, &xl_mii_bitbang_ops, phy, reg));
430 xl_miibus_writereg(device_t dev, int phy, int reg, int data) argument
439 mii_bitbang_writereg(dev, &xl_mii_bitbang_ops, phy, reg, data);
1075 int error = 0, phy, rid, res, unit; local
1398 phy = MII_PHY_ANY;
1400 phy = 24;
1402 xl_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY,
/freebsd-12-stable/sys/dev/ste/
H A Dif_ste.c238 ste_miibus_readreg(device_t dev, int phy, int reg) argument
241 return (mii_bitbang_readreg(dev, &ste_mii_bitbang_ops, phy, reg));
245 ste_miibus_writereg(device_t dev, int phy, int reg, int data) argument
248 mii_bitbang_writereg(dev, &ste_mii_bitbang_ops, phy, reg, data);
910 int error = 0, phy, pmc, prefer_iomap, rid; local
999 phy = MII_PHY_ANY;
1001 phy = 0;
1003 ste_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
/freebsd-12-stable/sys/dev/bm/
H A Dif_bm.c201 bm_miibus_readreg(device_t dev, int phy, int reg) argument
204 return (mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg));
208 bm_miibus_writereg(device_t dev, int phy, int reg, int data) argument
211 mii_bitbang_readreg(dev, &bm_mii_bitbang_ops, phy, reg);
/freebsd-12-stable/sys/dev/dwc/
H A Dif_dwc.c1179 "Can't find gpio controller for phy reset\n");
1186 device_printf(dev, "Can't map gpio for phy reset\n");
1277 if (OF_getprop_alloc(node, "phy-mode", (void **)&phy_mode)) {
1394 dwc_miibus_read_reg(device_t dev, int phy, int reg) argument
1403 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
1422 dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) argument
1430 mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT)
/freebsd-12-stable/sys/dev/ffec/
H A Dif_ffec.c47 * phy-mode = "rgmii";
48 * phy-disable-preamble; // optional
51 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii".
52 * There is also an optional property, phy-disable-preamble, which if present
318 ffec_miibus_readreg(device_t dev, int phy, int reg) argument
329 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
343 ffec_miibus_writereg(device_t dev, int phy, int reg, int val) argument
353 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
1507 device_printf(sc->dev, "No valid 'phy-mode' "
1727 if (OF_hasprop(ofw_node, "phy
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/freebsd-12-stable/sys/dev/altera/atse/
H A Dif_atse.c1501 atse_miibus_readreg(device_t dev, int phy, int reg) argument
1510 * but de-facto hard-code the phy#.
1512 if (phy != sc->atse_phy_addr) {
1522 atse_miibus_writereg(device_t dev, int phy, int reg, int data) argument
1530 * but de-facto hard-code the phy#.
1532 if (phy != sc->atse_phy_addr) {
/freebsd-12-stable/sys/dev/isci/scil/
H A Dscic_sds_remote_device.c172 //Get accurate port width from port's phy mask for a DA device.
907 SCIC_SDS_PHY_T * phy; local
910 phy = scic_sds_port_get_a_connected_phy(this_device->owning_port);
911 scic_sata_phy_get_properties(phy, &properties);
/freebsd-12-stable/sys/dev/ral/
H A Drt2860reg.h823 uint16_t phy; member in struct:rt2860_txwi
893 uint16_t phy; member in struct:rt2860_rxwi
980 enum ieee80211_phytype phy; member in struct:rt2860_rate
/freebsd-12-stable/sys/dev/usb/wlan/
H A Dif_zyd.c1075 static const struct zyd_phy_pair phy[] = ZYD_AL2230_PHY_FINI_PART1; local
1077 for (i = 0; i < nitems(phy); i++)
1078 zyd_write16_m(sc, phy[i].reg, phy[i].val);
2443 uint8_t phy; local
2486 phy = zyd_plcp_signal(sc, rate);
2487 desc->phy = phy;
2489 desc->phy |= ZYD_TX_PHY_OFDM;
2491 desc->phy |
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