/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/MCA/ |
H A D | Instruction.h | 503 void setUsedBuffers(uint64_t Mask) { UsedBuffers = Mask; } argument
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonStoreWidening.cpp | 410 unsigned Mask = (0xFFFFFFFFU >> (32-NBits)); local 411 unsigned Val = (SO.getImm() & Mask) << Shift;
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H A D | HexagonExpandCondsets.cpp | 296 unsigned Mask = getMaskForSub(RR.Sub) | Exec; local 299 Map.insert(std::make_pair(RR.Reg, Mask)); 301 F->second |= Mask; 309 unsigned Mask = getMaskForSub(RR.Sub) | Exec; local 310 if (Mask & F->second)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsAsmBackend.cpp | 290 uint64_t Mask = ((uint64_t)(-1) >> local 292 CurVal |= Value & Mask;
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 352 unsigned &SrcReg2, int &Mask, int &Value) const override; 355 unsigned SrcReg2, int Mask, int Value,
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H A D | PPCRegisterInfo.h | 92 void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
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H A D | PPCInstrInfo.cpp | 1591 unsigned &SrcReg2, int &Mask, 1604 Mask = 0xFFFF; 1615 Mask = 0; 1621 unsigned SrcReg2, int Mask, int Value, 1924 uint64_t Mask = ~0LLU; 1927 Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1); 1929 Mask >>= MBInLoHWord ? 0 : 16; 1938 Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1); 1939 Mask >>= 16; 1943 if (Mask ! [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | RegisterCoalescer.cpp | 948 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntA.reg); local 949 IntA.createSubRangeFrom(Allocator, Mask, IntA); 951 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntB.reg); local 952 IntB.createSubRangeFrom(Allocator, Mask, IntB); 1656 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubRegIdx); local 1658 Mask = ~Mask; 1661 if ((S.LaneMask & Mask).none()) 3376 LaneBitmask Mask = DstIdx == 0 ? CP.getNewRC()->getLaneMask() local 3379 assert(Mask 3384 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(DstIdx, R.LaneMask); local 3394 LaneBitmask Mask = SrcIdx == 0 ? CP.getNewRC()->getLaneMask() local 3400 LaneBitmask Mask = TRI->composeSubRegIndexLaneMask(SrcIdx, R.LaneMask); local [all...] |
H A D | MachineSink.cpp | 1215 LaneBitmask Mask; local 1217 Mask |= (*S).second; 1219 SuccBB->addLiveIn(SrcReg, Mask.any() ? Mask : LaneBitmask::getAll());
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 969 uint64_t Mask = ((uint64_t)(-1LL) >> (64 - Size)), OrigMask = Mask; local 973 if (Imm == 0 || Imm == Mask || 974 AArch64_AM::isLogicalImmediate(Imm & Mask, Size)) 999 NewImm = (Imm | Ones) & Mask; 1004 if (isShiftedMask_64(NewImm) || isShiftedMask_64(~(NewImm | ~Mask))) 1012 Mask >>= EltSize; 1016 if (((Imm ^ Hi) & (DemandedBits & DemandedBitsHi) & Mask) != 0) 1102 /// Mask are known to be either zero or one and return them Known. 1157 APInt Mask local 1161 APInt Mask = APInt::getHighBitsSet(BitWidth, BitWidth - 16); local 4284 const uint32_t *Mask; local 4645 const uint32_t *Mask = TRI->getTLSCallPreservedMask(); local 5013 uint64_t Mask = LHS.getConstantOperandVal(1); local 5029 uint64_t Mask = LHS.getConstantOperandVal(1); local 5040 uint64_t Mask = LHS.getValueSizeInBits() - 1; local 5050 uint64_t Mask = LHS.getValueSizeInBits() - 1; local 6982 isConcatMask(ArrayRef<int> Mask, EVT VT, bool SplitLHS) argument 7007 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Op)->getMask(); local 8617 const uint32_t *Mask = TRI->getWindowsStackProbePreservedMask(); local 9317 auto Mask = SVI->getShuffleMask(); local 10246 SDValue Mask = N->getOperand(1); local 10821 tryCombineCRC32(unsigned Mask, SDNode *N, SelectionDAG &DAG) argument 12268 SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask); local 13274 ConstantInt* Mask = dyn_cast<ConstantInt>(AndI.getOperand(1)); local [all...] |
H A D | AArch64ISelDAGToDAG.cpp | 2014 APInt Mask(UsefulBits); 2015 Mask.clearAllBits(); 2016 Mask.flipAllBits(); 2021 Mask <<= ShiftAmt; 2022 getUsefulBits(Op, Mask, Depth + 1); 2023 Mask.lshrInPlace(ShiftAmt); 2029 Mask.lshrInPlace(ShiftAmt); 2030 getUsefulBits(Op, Mask, Depth + 1); 2031 Mask <<= ShiftAmt; 2035 UsefulBits &= Mask; 2249 isShiftedMask(uint64_t Mask, EVT VT) argument [all...] |
H A D | AArch64FastISel.cpp | 1685 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; local 1686 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); 1731 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; local 1732 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); 1774 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff; local 1775 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask); 3981 uint64_t Mask = 0; local 3987 Mask = 0x1; 3990 Mask = 0xff; 3993 Mask 4090 uint64_t Mask = 0; local 4196 uint64_t Mask = 0; local 4317 uint64_t Mask = 0; local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | MachineInstr.h | 323 unsigned Mask = BundledPred | BundledSucc; local 324 Flags = (Flags & Mask) | (flags & ~Mask); 1685 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const;
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H A D | StackMaps.h | 310 LiveOutVec parseRegisterLiveOutMask(const uint32_t *Mask) const;
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/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/fuzzer/ |
H A D | FuzzerMutate.cpp | 528 // Mask represents the set of Data bytes that are worth mutating. 531 const Vector<uint8_t> &Mask) { 532 size_t MaskedSize = std::min(Size, Mask.size()); 542 if (Mask[I]) 552 if (Mask[I])
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H A D | FuzzerMutate.h | 74 /// that have '1' in Mask. 75 /// Mask.size() should be >= Size. 77 const Vector<uint8_t> &Mask);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DwarfExpression.h | 251 void addAnd(unsigned Mask);
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/freebsd-12-stable/contrib/llvm-project/llvm/tools/llvm-readobj/ |
H A D | ARMWinEHPrinter.h | 29 uint8_t Mask; member in struct:llvm::ARM::WinEH::Decoder::RingEntry
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/freebsd-12-stable/sys/contrib/dev/acpica/include/ |
H A D | acresrc.h | 431 UINT16 Mask,
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/freebsd-12-stable/stand/efi/include/ |
H A D | efipciio.h | 140 @param Mask Mask used for the polling criteria. 160 IN UINT64 Mask,
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
H A D | SystemZInstrInfo.cpp | 517 unsigned &SrcReg2, int &Mask, 526 Mask = ~0; 1563 // Return true if Mask matches the regexp 0*1+0*, given that zero masks 1566 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) { argument 1567 unsigned First = findFirstSet(Mask); 1568 uint64_t Top = (Mask >> First) + 1; 1577 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize, argument 1580 Mask &= allOnes(BitSize); 1581 if (Mask == 0) 1587 if (isStringOfOnes(Mask, LS 516 analyzeCompare(const MachineInstr &MI, unsigned &SrcReg, unsigned &SrcReg2, int &Mask, int &Value) const argument [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Analysis/ |
H A D | TargetTransformInfo.cpp | 868 SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1); 873 Mask[i] = val; 876 return Mask == ActualMask; 1140 SmallVector<int, 16> Mask = Shuffle->getShuffleMask(); local 1141 if (ShuffleMask != Mask)
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMELFStreamer.cpp | 1456 uint32_t Mask = 0; 1462 if ((Mask & Bit) == 0) { 1463 Mask |= Bit; 1477 UnwindOpAsm.EmitVFPRegSave(Mask); 1479 UnwindOpAsm.EmitRegSave(Mask);
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.cpp | 498 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); local 500 if (!Mask) 503 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 506 return SDValue(); // Mask+1 is not a power of 2 620 APInt Mask, InvMask; local 626 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) { 631 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 634 Mask.getBitWidth() == InvMask.getBitWidth() && Mask 1617 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), local 1632 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), local [all...] |
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | IRBuilder.h | 710 CallInst *CreateMaskedLoad(Value *Ptr, unsigned Align, Value *Mask, 715 Value *Mask); 719 Value *Mask = nullptr, 725 Value *Mask = nullptr); 2547 Value *CreateShuffleVector(Value *V1, Value *V2, Value *Mask, argument 2551 if (auto *MC = dyn_cast<Constant>(Mask)) 2553 return Insert(new ShuffleVectorInst(V1, V2, Mask), Name); 2558 Value *Mask = ConstantDataVector::get(Context, IntMask); local 2559 return CreateShuffleVector(V1, V2, Mask, Name); 2793 /// represents an alignment assumption on the provided Ptr, Mask, Typ 2796 CreateAlignmentAssumptionHelper(const DataLayout &DL, Value *PtrValue, Value *Mask, Type *IntPtrTy, Value *OffsetValue, Value **TheCheck) argument 2844 Value *Mask = ConstantInt::get(IntPtrTy, Alignment - 1); local 2874 Value *Mask = CreateSub(Alignment, ConstantInt::get(IntPtrTy, 1), "mask"); local [all...] |