Lines Matching refs:Mask
1685 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1686 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1731 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1732 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
1774 uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;
1775 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
3981 uint64_t Mask = 0;
3987 Mask = 0x1;
3990 Mask = 0xff;
3993 Mask = 0xffff;
4000 ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);
4090 uint64_t Mask = 0;
4093 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break;
4094 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break;
4102 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
4108 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4196 uint64_t Mask = 0;
4199 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break;
4200 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break;
4208 Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);
4209 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
4215 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);
4317 uint64_t Mask = 0;
4320 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break;
4321 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break;
4330 Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
4336 ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);