Searched refs:CSR_WRITE_2 (Results 26 - 50 of 68) sorted by relevance

123

/freebsd-12-stable/sys/dev/stge/
H A Dif_stge.c403 CSR_WRITE_2(sc, STGE_EepromCtrl,
1316 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1324 CSR_WRITE_2(sc, STGE_IntEnable,
1513 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2020 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2021 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2022 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2064 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2071 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2096 CSR_WRITE_2(s
[all...]
/freebsd-12-stable/sys/dev/ep/
H A Dif_epreg.h65 #define GO_WINDOW(sc, x) CSR_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT|(x))
336 #define SET_IRQ(sc, irq) CSR_WRITE_2((sc), EP_W0_RESOURCE_CFG, \
/freebsd-12-stable/sys/dev/wi/
H A Dif_wi_pccard.c196 CSR_WRITE_2(sc, WI_INT_EN, 0);
197 CSR_WRITE_2(sc, WI_EVENT_ACK, 0xFFFF);
/freebsd-12-stable/sys/dev/vr/
H A Dif_vr.c276 CSR_WRITE_2(sc, VR_MIIDATA, data);
731 CSR_WRITE_2(sc, VR_ISR, 0xFFFF);
732 CSR_WRITE_2(sc, VR_IMR, 0);
734 CSR_WRITE_2(sc, VR_MII_IMR, 0);
1610 CSR_WRITE_2(sc, VR_ISR, status);
1674 CSR_WRITE_2(sc, VR_IMR, 0x0000);
1705 CSR_WRITE_2(sc, VR_IMR, 0);
1706 CSR_WRITE_2(sc, VR_ISR, status);
1711 CSR_WRITE_2(sc, VR_ISR, status);
1737 CSR_WRITE_2(s
[all...]
H A Dif_vrreg.h754 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val) macro
763 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
764 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd-12-stable/sys/dev/rl/
H A Dif_rl.c470 CSR_WRITE_2(sc, rl8139_reg, data);
1217 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16);
1328 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD);
1331 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD);
1474 CSR_WRITE_2(sc, RL_ISR, status);
1513 CSR_WRITE_2(sc, RL_IMR, 0);
1515 CSR_WRITE_2(sc, RL_ISR, status);
1539 CSR_WRITE_2(sc, RL_IMR, RL_INTRS);
1751 CSR_WRITE_2(sc, RL_IMR, 0);
1755 CSR_WRITE_2(s
[all...]
H A Dif_rlreg.h950 #define CSR_WRITE_2(sc, reg, val) \ macro
972 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
975 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd-12-stable/sys/dev/re/
H A Dif_re.c614 CSR_WRITE_2(sc, re8139_reg, data);
822 CSR_WRITE_2(sc, RL_ISR, RL_INTRS);
839 CSR_WRITE_2(sc, RL_ISR, 0xFFFF);
851 CSR_WRITE_2(sc, RL_ISR, status);
2541 CSR_WRITE_2(sc, RL_ISR, status);
2570 CSR_WRITE_2(sc, RL_IMR, 0);
2591 CSR_WRITE_2(sc, RL_ISR, status);
2644 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS);
2665 CSR_WRITE_2(sc, RL_IMR, 0);
2673 CSR_WRITE_2(s
[all...]
/freebsd-12-stable/sys/dev/msk/
H A Dif_msk.c689 CSR_WRITE_2(sc_if->msk_softc,
754 CSR_WRITE_2(sc_if->msk_softc,
822 CSR_WRITE_2(sc_if->msk_softc,
1296 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1310 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1312 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1369 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1373 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1378 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1379 CSR_WRITE_2(s
[all...]
/freebsd-12-stable/sys/dev/bwi/
H A Dif_bwivar.h84 #define CSR_WRITE_2(sc, reg, val) \ macro
90 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
95 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
100 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
/freebsd-12-stable/sys/dev/fxp/
H A Dif_fxpvar.h250 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) macro
H A Dif_fxp.c1151 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1153 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1155 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1173 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS);
1187 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1189 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1191 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1206 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK);
1210 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg);
1213 CSR_WRITE_2(s
[all...]
/freebsd-12-stable/sys/dev/vx/
H A Dif_vx_pci.c164 CSR_WRITE_2(sc, VX_W0_EEPROM_COMMAND,
H A Dif_vxreg.h63 #define GO_WINDOW(x) CSR_WRITE_2(sc, VX_COMMAND, WINDOW_SELECT|(x))
/freebsd-12-stable/sys/dev/sn/
H A Dif_snreg.h401 #define SMC_SELECT_BANK(sc, x) { CSR_WRITE_2(sc, BANK_SELECT_REG_W, (x)); }
H A Dif_sn_pccard.c304 CSR_WRITE_2(sc, IAR_ADDR0_REG_W + i * 2, w);
/freebsd-12-stable/sys/dev/ipw/
H A Dif_ipwreg.h339 #define CSR_WRITE_2(sc, reg, val) \ macro
367 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd-12-stable/sys/dev/iwi/
H A Dif_iwireg.h589 #define CSR_WRITE_2(sc, reg, val) \ macro
609 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd-12-stable/sys/dev/age/
H A Dif_agevar.h241 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-12-stable/sys/dev/alc/
H A Dif_alcvar.h264 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-12-stable/sys/dev/ale/
H A Dif_alevar.h233 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd-12-stable/sys/dev/vge/
H A Dif_vge.c409 CSR_WRITE_2(sc, VGE_MIIDATA, data);
1595 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT,
2004 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0);
2086 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1);
2090 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1);
2091 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT);
2101 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0);
2111 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF);
2413 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF);
/freebsd-12-stable/sys/dev/xl/
H A Dif_xlreg.h656 #define CSR_WRITE_2(sc, reg, val) \ macro
674 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \
/freebsd-12-stable/sys/dev/wb/
H A Dif_wbreg.h376 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->wb_res, reg, val) macro
/freebsd-12-stable/sys/dev/sge/
H A Dif_sge.c185 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->sge_res, reg, val) macro
481 CSR_WRITE_2(sc, RxMacControl, rxfilt);
502 CSR_WRITE_2(sc, RxMacControl, rxfilt);
1660 CSR_WRITE_2(sc, RxMPSControl, ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN +
1667 CSR_WRITE_2(sc, RxMacControl, rxfilt);

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