1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer. 2. The name
10 * of the author may not be used to endorse or promote products derived from
11 * this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
16 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
17 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
18 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
19 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
20 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
21 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
22 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * $FreeBSD$
25 */
26
27/*
28 * DELAY_MULTIPLE: How much to boost "base" delays, except
29 * for the inter-bit delays in get_eeprom_data.  A cyrix Media GX needed this.
30 */
31#define DELAY_MULTIPLE 10
32#define BIT_DELAY_MULTIPLE 10
33
34/*
35 * Some global constants
36 */
37#define TX_INIT_RATE         16
38#define TX_INIT_MAX_RATE     64
39#define RX_INIT_LATENCY      64
40#define RX_INIT_EARLY_THRESH 208/* not less than MINCLSIZE */
41#define RX_NEXT_EARLY_THRESH 500
42
43#define EEPROMSIZE      0x40
44#define MAX_EEPROMBUSY  1000
45#define EP_LAST_TAG     0xd7
46#define EP_MAX_BOARDS   16
47#define EP_IOSIZE	16	/* 16 bytes of I/O space used. */
48
49/*
50 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
51 * Offset 0xa)
52 */
53#define EEPROM_CMD_RD    0x0080	/* Read:  Address required (5 bits) */
54#define EEPROM_CMD_WR    0x0040	/* Write: Address required (5 bits) */
55#define EEPROM_CMD_ERASE 0x00c0	/* Erase: Address required (5 bits) */
56#define EEPROM_CMD_EWEN  0x0030	/* Erase/Write Enable: No data required */
57
58#define EEPROM_BUSY		(1<<15)
59#define EEPROM_TST_MODE		(1<<14)
60
61/*
62 * Some short functions, worth to let them be a macro
63 */
64#define is_eeprom_busy(sc) (CSR_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
65#define GO_WINDOW(sc, x)	CSR_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT|(x))
66
67/**************************************************************************
68 *									  *
69 * These define the EEPROM data structure.  They are used in the probe
70 * function to verify the existence of the adapter after having sent
71 * the ID_Sequence.
72 *
73 **************************************************************************/
74
75#define EEPROM_NODE_ADDR_0	0x0	/* Word */
76#define EEPROM_NODE_ADDR_1	0x1	/* Word */
77#define EEPROM_NODE_ADDR_2	0x2	/* Word */
78#define EEPROM_PROD_ID		0x3	/* 0x9[0-f]50 */
79#define EEPROM_MFG_DATE         0x4	/* Manufacturing date */
80#define EEPROM_MFG_DIVSION      0x5	/* Manufacturing division */
81#define EEPROM_MFG_PRODUCT      0x6	/* Product code */
82#define EEPROM_MFG_ID		0x7	/* 0x6d50 */
83#define EEPROM_ADDR_CFG		0x8	/* Base addr */
84#define ADDR_CFG_EISA		0x1f
85#define ADDR_CFG_MASK		0x1f
86#define EEPROM_RESOURCE_CFG	0x9	/* IRQ. Bits 12-15 */
87#define EEPROM_OEM_ADDR0        0xa
88#define EEPROM_OEM_ADDR1        0xb
89#define EEPROM_OEM_ADDR2        0xc
90#define EEPROM_SOFTINFO         0xd
91#define EEPROM_COMPAT           0xe
92#define EEPROM_SOFTINFO2        0xf
93#define EEPROM_CAP              0x10
94#define CAP_ISA		0x2083
95#define CAP_PCMCIA		0x2082
96#define EEPROM_INT_CONFIG_0	0x12
97#define EEPROM_INT_CONFIG_1	0x13
98/* RAM Partition TX FIFO/RX FIFO */
99#define ICW1_RAM_PART_MASK	0x03
100#define ICW1_RAM_PART_35	0x00	/* 2:5 (only legal if RAM size == 000b
101					 * default power-up/reset */
102#define ICW1_RAM_PART_13	0x01	/* 1:3 (only legal if RAM size ==
103					 * 000b) */
104#define ICW1_RAM_PART_11	0x10	/* 1:1		 */
105#define ICW1_RAM_PART_RESV	0x11	/* Reserved	 */
106/* ISA Adapter Selection */
107#define ICW1_IAS_MASK		0x0c
108#define ICW1_IAS_DIS		0x00	/* Both mechanisms disabled (default) */
109#define ICW1_IAS_ISA		0x04	/* ISA contention only */
110#define ICW1_IAS_PNP		0x08	/* ISA Plug and Play only */
111#define ICW1_IAS_BOTH		0x0c	/* Both mechanisms enabled */
112
113#define EEPROM_CHECKSUM_EL3     0x17
114
115/**************************************************************************
116 *									  *
117 * These are the registers for the 3Com 3c509 and their bit patterns when *
118 * applicable.  They have been taken out the "EtherLink III Parallel      *
119 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
120 * from 3com.								  *
121 *									  *
122 **************************************************************************/
123
124#define EP_COMMAND		0x0e	/* Write. BASE+0x0e is always a
125					 * command reg. */
126#define EP_STATUS		0x0e	/* Read. BASE+0x0e is always status
127					 * reg. */
128#define EP_WINDOW		0x0f	/* Read. BASE+0x0f is always window
129					 * reg. */
130/*
131 * Window 0 registers. Setup.
132 */
133/* Write */
134#define EP_W0_EEPROM_DATA	0x0c
135#define EP_W0_EEPROM_COMMAND	0x0a
136#define EP_W0_RESOURCE_CFG	0x08
137#define EP_W0_ADDRESS_CFG	0x06
138#define EP_W0_CONFIG_CTRL	0x04
139	/* Read */
140#define EP_W0_PRODUCT_ID	0x02
141#define EP_W0_MFG_ID		0x00
142
143/*
144 * Window 1 registers. Operating Set.
145 */
146/* Write */
147#define EP_W1_TX_PIO_WR_2	0x02
148#define EP_W1_TX_PIO_WR_1	0x00
149/* Read */
150#define EP_W1_FREE_TX		0x0c
151#define EP_W1_TX_STATUS		0x0b	/* byte */
152#define EP_W1_TIMER		0x0a	/* byte */
153#define EP_W1_RX_STATUS		0x08
154#define EP_W1_RX_PIO_RD_2	0x02
155#define EP_W1_RX_PIO_RD_1	0x00
156
157/*
158 * Window 2 registers. Station Address Setup/Read
159 */
160/* Read/Write */
161#define EP_W2_PHY_MGMT		0x0c
162#define EP_W2_ALT_EEPROM	0x0a
163#define EP_W2_ADDR_5		0x05
164#define EP_W2_ADDR_4		0x04
165#define EP_W2_ADDR_3		0x03
166#define EP_W2_ADDR_2		0x02
167#define EP_W2_ADDR_1		0x01
168#define EP_W2_ADDR_0		0x00
169
170/*
171 * Window 3 registers.  FIFO Management.
172 */
173/* Read */
174#define EP_W3_FREE_TX		0x0c
175#define EP_W3_FREE_RX		0x0a
176#define EP_W3_OPTIONS		0x08
177
178/*
179 * Window 4 registers. Diagnostics.
180 */
181/* Read/Write */
182#define EP_W4_MEDIA_TYPE	0x0a
183#define EP_W4_CTRLR_STATUS	0x08
184#define EP_W4_NET_DIAG		0x06
185#define EP_W4_FIFO_DIAG		0x04
186#define EP_W4_HOST_DIAG		0x02
187#define EP_W4_TX_DIAG		0x00
188
189/*
190 * Window 5 Registers.  Results and Internal status.
191 */
192/* Read */
193#define EP_W5_READ_0_MASK	0x0c
194#define EP_W5_INTR_MASK		0x0a
195#define EP_W5_RX_FILTER		0x08
196#define EP_W5_RX_EARLY_THRESH	0x06
197#define EP_W5_TX_AVAIL_THRESH	0x02
198#define EP_W5_TX_START_THRESH	0x00
199
200/*
201 * Window 6 registers. Statistics.
202 */
203/* Read/Write */
204#define TX_TOTAL_OK		0x0c
205#define RX_TOTAL_OK		0x0a
206#define TX_DEFERRALS		0x08
207#define RX_FRAMES_OK		0x07
208#define TX_FRAMES_OK		0x06
209#define RX_OVERRUNS		0x05
210#define TX_COLLISIONS		0x04
211#define TX_AFTER_1_COLLISION	0x03
212#define TX_AFTER_X_COLLISIONS	0x02
213#define TX_NO_SQE		0x01
214#define TX_CD_LOST		0x00
215
216/****************************************
217 *
218 * Register definitions.
219 *
220 ****************************************/
221
222/*
223 * Command parameter that disables threshold interrupts
224 *   PIO (3c509) cards use 2044.  The fifo word-oriented and 2044--2047 work.
225 *  "busmastering" cards need 8188.
226 * The implicit two-bit upshift done by busmastering cards means
227 * a value of 2047 disables threshold interrupts on both.
228 */
229#define EP_THRESH_DISABLE    2047
230
231/*
232 * Command register. All windows.
233 *
234 * 16 bit register.
235 *     15-11:  5-bit code for command to be executed.
236 *     10-0:   11-bit arg if any. For commands with no args;
237 *	      this can be set to anything.
238 */
239#define GLOBAL_RESET		(u_short) 0x0000	/* Wait at least 1ms
240							 * after issuing */
241#define WINDOW_SELECT		(u_short) (0x1<<11)
242#define START_TRANSCEIVER	(u_short) (0x2<<11)	/* Read ADDR_CFG reg to
243							 * determine whether
244							 * this is needed. If
245							 * so; wait 800 uSec
246							 * before using trans-
247							 * ceiver. */
248#define RX_DISABLE		(u_short) (0x3<<11)	/* state disabled on
249							 * power-up */
250#define RX_ENABLE		(u_short) (0x4<<11)
251#define RX_RESET		(u_short) (0x5<<11)
252#define RX_DISCARD_TOP_PACK	(u_short) (0x8<<11)
253#define TX_ENABLE		(u_short) (0x9<<11)
254#define TX_DISABLE		(u_short) (0xa<<11)
255#define TX_RESET		(u_short) (0xb<<11)
256#define REQ_INTR		(u_short) (0xc<<11)
257/*
258 * The following C_* acknowledge the various interrupts. Some of them don't
259 * do anything.  See the manual.
260 */
261#define ACK_INTR		(u_short) (0x6800)
262#	define C_INTR_LATCH	(u_short) (ACK_INTR|0x1)
263#	define C_CARD_FAILURE	(u_short) (ACK_INTR|0x2)
264#	define C_TX_COMPLETE	(u_short) (ACK_INTR|0x4)
265#	define C_TX_AVAIL	(u_short) (ACK_INTR|0x8)
266#	define C_RX_COMPLETE	(u_short) (ACK_INTR|0x10)
267#	define C_RX_EARLY	(u_short) (ACK_INTR|0x20)
268#	define C_INT_RQD		(u_short) (ACK_INTR|0x40)
269#	define C_UPD_STATS	(u_short) (ACK_INTR|0x80)
270#define SET_INTR_MASK		(u_short) (0xe<<11)
271#define SET_RD_0_MASK		(u_short) (0xf<<11)
272#define SET_RX_FILTER		(u_short) (0x10<<11)
273#	define FIL_INDIVIDUAL	(u_short) (0x1)
274#	define FIL_MULTICAST     (u_short) (0x02)
275#	define FIL_BRDCST        (u_short) (0x04)
276#	define FIL_PROMISC       (u_short) (0x08)
277#define SET_RX_EARLY_THRESH	(u_short) (0x11<<11)
278#define SET_TX_AVAIL_THRESH	(u_short) (0x12<<11)
279#define SET_TX_START_THRESH	(u_short) (0x13<<11)
280#define STATS_ENABLE		(u_short) (0x15<<11)
281#define STATS_DISABLE		(u_short) (0x16<<11)
282#define STOP_TRANSCEIVER	(u_short) (0x17<<11)
283#define TX_PLL_ENABLE		(u_short) (0x18<<11)
284#define TX_PLL_DISABLE		(u_short) (0x19<<11)
285#define POWER_UP		(u_short) (0x1b<<11)
286#define POWER_DOWN		(u_short) (0x1b<<11)
287#define POWER_AUTO		(u_short) (0x1b<<11)
288
289/*
290 * Status register. All windows.
291 *
292 *     15-13:  Window number(0-7).
293 *     12:     Command_in_progress.
294 *     11:     reserved.
295 *     10:     reserved.
296 *     9:      reserved.
297 *     8:      reserved.
298 *     7:      Update Statistics.
299 *     6:      Interrupt Requested.
300 *     5:      RX Early.
301 *     4:      RX Complete.
302 *     3:      TX Available.
303 *     2:      TX Complete.
304 *     1:      Adapter Failure.
305 *     0:      Interrupt Latch.
306 */
307#define S_INTR_LATCH		(u_short) (0x1)
308#define S_CARD_FAILURE		(u_short) (0x2)
309#define S_TX_COMPLETE		(u_short) (0x4)
310#define S_TX_AVAIL		(u_short) (0x8)
311#define S_RX_COMPLETE		(u_short) (0x10)
312#define S_RX_EARLY		(u_short) (0x20)
313#define S_INT_RQD		(u_short) (0x40)
314#define S_UPD_STATS		(u_short) (0x80)
315#define S_MASK	(u_short) 0xFF	/* mask of S_* */
316#define S_5_INTS                (S_CARD_FAILURE|S_TX_COMPLETE|\
317				 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
318#define S_COMMAND_IN_PROGRESS	(u_short) (0x1000)
319
320#define EP_BUSY_WAIT(sc) while (CSR_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS)
321
322/* Address Config. Register.
323 * Window 0/Port 06
324 */
325
326#define ACF_CONNECTOR_BITS	14
327#define ACF_CONNECTOR_UTP	0
328#define ACF_CONNECTOR_AUI	1
329#define ACF_CONNECTOR_BNC	3
330
331/* Resource configuration register.
332 * Window 0/Port 08
333 *
334 */
335
336#define SET_IRQ(sc, irq) CSR_WRITE_2((sc), EP_W0_RESOURCE_CFG, \
337			((CSR_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) | \
338			((u_short)(irq)<<12))  )	/* set IRQ i */
339
340/*
341 * FIFO Registers.
342 * RX Status. Window 1/Port 08
343 *
344 *     15:     Incomplete or FIFO empty.
345 *     14:     1: Error in RX Packet   0: Incomplete or no error.
346 *     13-11:  Type of error.
347 *	      1000 = Overrun.
348 *	      1011 = Run Packet Error.
349 *	      1100 = Alignment Error.
350 *	      1101 = CRC Error.
351 *	      1001 = Oversize Packet Error (>1514 bytes)
352 *	      0010 = Dribble Bits.
353 *	      (all other error codes, no errors.)
354 *
355 *     10-0:   RX Bytes (0-1514)
356 */
357#define ERR_RX_INCOMPLETE  (u_short) (0x1<<15)
358#define ERR_RX		   (u_short) (0x1<<14)
359#define ERR_RX_OVERRUN 	   (u_short) (0x8<<11)
360#define ERR_RX_RUN_PKT	   (u_short) (0xb<<11)
361#define ERR_RX_ALIGN	   (u_short) (0xc<<11)
362#define ERR_RX_CRC	   (u_short) (0xd<<11)
363#define ERR_RX_OVERSIZE	   (u_short) (0x9<<11)
364#define ERR_RX_DRIBBLE	   (u_short) (0x2<<11)
365
366/*
367 * FIFO Registers.
368 * TX Status. Window 1/Port 0B
369 *
370 *   Reports the transmit status of a completed transmission. Writing this
371 *   register pops the transmit completion stack.
372 *
373 *   Window 1/Port 0x0b.
374 *
375 *     7:      Complete
376 *     6:      Interrupt on successful transmission requested.
377 *     5:      Jabber Error (TP Only, TX Reset required. )
378 *     4:      Underrun (TX Reset required. )
379 *     3:      Maximum Collisions.
380 *     2:      TX Status Overflow.
381 *     1-0:    Undefined.
382 *
383 */
384#define TXS_COMPLETE		0x80
385#define TXS_SUCCES_INTR_REQ		0x40
386#define TXS_JABBER		0x20
387#define TXS_UNDERRUN		0x10
388#define TXS_MAX_COLLISION	0x8
389#define TXS_STATUS_OVERFLOW	0x4
390
391/*
392 * Configuration control register.
393 * Window 0/Port 04
394 */
395/* Read */
396#define IS_AUI 				(1<<13)
397#define IS_BNC 				(1<<12)
398#define IS_UTP 				(1<<9)
399/* Write */
400#define ENABLE_DRQ_IRQ			0x0001
401#define W0_P4_CMD_RESET_ADAPTER       0x4
402#define W0_P4_CMD_ENABLE_ADAPTER      0x1
403
404/*
405 * Media type and status.
406 * Window 4/Port 0A
407 */
408#define JABBER_GUARD_ENABLE	0x40
409#define LINKBEAT_ENABLE		0x80
410#define	ENABLE_UTP		(JABBER_GUARD_ENABLE | LINKBEAT_ENABLE)
411#define DISABLE_UTP		0x0
412#define	MT_CSD			0x0004	/* CRC Strip disable */
413#define	MT_SQE			0x0008	/* SQE Enable */
414#define	MT_C0			0x0010	/* Collison */
415#define	MT_CS			0x0020	/* Carrier Sense */
416#define MT_J			0x0200	/* Jabber detected */
417#define MT_PL			0x0400	/* Plarity Inverted */
418#define MT_LB			0x0800	/* Link Beat detected */
419#define MT_SQ			0x1000	/* SQE Present */
420#define MT_IN			0x2000	/* Reserved */
421#define MT_CE			0x4000	/* Coax */
422#define MT_TPE			0x8000
423
424/*
425 * Misc defines for various things.
426 */
427#define ACTIVATE_ADAPTER_TO_CONFIG 	0xff	/* to the id_port */
428#define MFG_ID 				0x6d50	/* in EEPROM and W0
429						 * ADDR_CONFIG */
430#define PROD_ID 			0x9150
431
432#define AUI 				0x1
433#define BNC 				0x2
434#define UTP 				0x4
435
436#define RX_BYTES_MASK			(u_short) (0x07ff)
437