Lines Matching refs:CSR_WRITE_2
403 CSR_WRITE_2(sc, STGE_EepromCtrl,
1316 CSR_WRITE_2(sc, STGE_IntEnable, 0);
1324 CSR_WRITE_2(sc, STGE_IntEnable,
1513 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2020 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0]));
2021 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1]));
2022 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2]));
2064 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh);
2071 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff);
2096 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2099 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable);
2112 CSR_WRITE_2(sc, STGE_FlowOnTresh, 29696 / 16);
2113 CSR_WRITE_2(sc, STGE_FlowOffThresh, 3056 / 16);
2119 CSR_WRITE_2(sc, STGE_MaxFrameSize, sc->sc_if_framesize);
2135 CSR_WRITE_2(sc, STGE_DebugCtrl,
2139 CSR_WRITE_2(sc, STGE_DebugCtrl,
2142 CSR_WRITE_2(sc, STGE_DebugCtrl,
2223 CSR_WRITE_2(sc, STGE_IntEnable, 0);
2507 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2530 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);
2573 CSR_WRITE_2(sc, STGE_ReceiveMode, mode);