/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 833 case ISD::SHL: { 1210 case ISD::SHL:
|
H A D | SystemZISelLowering.cpp | 325 setOperationAction(ISD::SHL, VT, Custom); 1764 if (C.Op0.getOpcode() == ISD::SHL && 1966 NewC.Op0.getOpcode() == ISD::SHL && 2399 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt); 2518 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi, 2666 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64, 3019 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT)); 3089 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr, 3104 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, 3193 SDValue BitShift = DAG.getNode(ISD::SHL, D [all...] |
/freebsd-11.0-release/usr.bin/xlint/lint1/ |
H A D | scan.l | 129 "<<" return (operator(T_SHFTOP, SHL));
|
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.cpp | 732 setOperationAction(ISD::SHL, VT, Expand); 1037 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 1038 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 1048 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 1049 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 1123 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1124 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1261 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1262 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1515 setOperationAction(ISD::SHL, MV [all...] |
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 1567 return selectBinaryOp(I, ISD::SHL); 1723 Opcode = ISD::SHL; 1733 if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
|
H A D | SelectionDAGBuilder.h | 790 void visitShl (const User &I) { visitShift(I, ISD::SHL); }
|
H A D | SelectionDAGDumper.cpp | 191 case ISD::SHL: return "shl";
|
H A D | LegalizeTypes.cpp | 1053 Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,
|
H A D | LegalizeFloatTypes.cpp | 246 ISD::SHL, dl, RVT, DAG.getConstant(1, dl, RVT), 263 DAG.getNode(ISD::SHL, dl, LVT, SignBit, 271 ISD::SHL, dl, LVT, DAG.getConstant(1, dl, LVT),
|
H A D | SelectionDAG.cpp | 2165 case ISD::SHL: 2560 case ISD::SHL: 3224 case ISD::SHL: return std::make_pair(C1 << C2, true); 3535 case ISD::SHL: 3823 case ISD::SHL: 3862 case ISD::SHL: 6995 case ISD::SHL:
|
H A D | SelectionDAGBuilder.cpp | 170 DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 2078 SDValue SwitchVal = DAG.getNode(ISD::SHL, dl, VT, 2381 if (Opcode == ISD::SRL || Opcode == ISD::SRA || Opcode == ISD::SHL) { 3069 IdxN = DAG.getNode(ISD::SHL, dl, 3786 ISD::SHL, dl, MVT::i32, IntegerPartOfX, 8079 if (!TLI.isOperationLegal(ISD::SHL, PTy))
|
H A D | LegalizeVectorTypes.cpp | 130 case ISD::SHL: 681 case ISD::SHL: 2066 case ISD::SHL:
|
/freebsd-11.0-release/contrib/llvm/lib/TableGen/ |
H A D | Record.cpp | 816 case SHL: 830 case SHL: Result = LHSv << RHSv; break; 857 case SHL: Result = "!shl"; break;
|
/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 368 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index, 407 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift); 476 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
|
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 726 if (Sub_1.getOpcode() == ISD::SHL) { 1175 case ISD::SHL: 1318 case ISD::SHL:
|
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelDAGToDAG.cpp | 1356 } else if (N->getOperand(0).getOpcode() == ISD::SHL) 1360 if (N->getOperand(0).getOpcode() == ISD::SHL)
|
H A D | SIISelLowering.cpp | 1907 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1); 2250 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
|
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 123 setOperationAction(ISD::SHL, VT, Custom); 615 setTargetDAGCombine(ISD::SHL); 4355 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 4389 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 4390 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 4396 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 4628 if (N->getOpcode() == ISD::SHL) 4657 // We can get here for a node like i32 = ISD::SHL i32, i64 6939 case ISD::SHL: 8840 DAG.getNode(ISD::SHL, D [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 337 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 1217 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, 1933 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, DL, MVT::i32)); 1942 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, DL, MVT::i32)); 2852 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi,
|
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 669 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom); 2307 case ISD::SHL: 4409 SDValue HiBitsForLo = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt); 4411 // Unfortunately, if ShAmt == 0, we just calculated "(SHL ShOpHi, 64)" which 4478 SDValue HiBitsForHi = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt); 4482 SDValue HiForBigShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); 4493 SDValue LoForNormalShift = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 6546 case ISD::SHL: 7437 DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 7446 DAG.getNode(ISD::SHL, D [all...] |
/freebsd-11.0-release/crypto/openssl/crypto/aes/asm/ |
H A D | aesp8-ppc.pl | 33 $SHL ="sldi"; 41 $SHL ="slwi"; 1454 $SHL $len,$len,4
|
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 613 setOperationAction(ISD::SHL, MVT::v2i64, Legal); 620 setOperationAction(ISD::SHL, MVT::v2i64, Expand); 1018 case PPCISD::SHL: return "PPCISD::SHL"; 5159 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal, 6645 "Unexpected SHL!"); 6656 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt); 6661 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5); 6663 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt); 6686 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, d [all...] |
/freebsd-11.0-release/contrib/llvm/include/llvm/TableGen/ |
H A D | Record.h | 731 enum BinaryOp : uint8_t { ADD, AND, SHL, SRA, SRL, LISTCONCAT,
|
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAGNodes.h | 1045 case ISD::SHL:
|
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | TargetLoweringBase.cpp | 1592 case Shl: return ISD::SHL;
|