Searched refs:R12 (Results 26 - 33 of 33) sorted by relevance
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| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 40 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 495 Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,
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| /freebsd-11.0-release/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 283 MSP430::R15, MSP430::R14, MSP430::R13, MSP430::R12
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| /freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 2003 return Primary ? X86::R11 : X86::R12;
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2926 .Case("ip", ARM::R12)
3299 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3300 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 868 ARM::R12, ARM::SP, ARM::LR, ARM::PC
956 Register = ARM::R12;
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| /freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 7912 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7926 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
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| /freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 5349 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5350 // This does not mean the MTCTR instruction must use R12; it's easier
5737 // On Darwin, R12 must contain the address of an indirect callee. This does
5738 // not mean the MTCTR instruction must use R12; it's easier to model this as
5745 PPC::R12), Callee));
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