/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyRegisterInfo.cpp | 58 MachineInstr &MI = *II; local 60 MachineBasicBlock &MBB = *MI.getParent(); 62 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 66 if (MI.mayLoadOrStore()) { 69 assert(FrameOffset >= 0 && MI.getOperand(1).getImm() >= 0); 70 int64_t Offset = MI.getOperand(1).getImm() + FrameOffset; 77 MI.getOperand(1).setImm(Offset); 78 MI.getOperand(2).ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false); 85 BuildMI(MBB, MI, MI [all...] |
H A D | WebAssemblyArgumentMove.cpp | 68 static bool IsArgument(const MachineInstr *MI) { argument 69 switch (MI->getOpcode()) { 92 MachineInstr *MI = MII; local 93 if (!IsArgument(MI)) { 102 MachineInstr *MI = I; local 103 if (IsArgument(MI)) { 104 EntryMBB.insert(InsertPt, MI->removeFromParent());
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/ |
H A D | DbgValueHistoryCalculator.cpp | 25 // \brief If @MI is a DBG_VALUE with debug value described by a 28 static unsigned isDescribedByReg(const MachineInstr &MI) { argument 29 assert(MI.isDebugValue()); 30 assert(MI.getNumOperands() == 4); 33 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : 0; 37 const MachineInstr &MI) { 40 assert(MI.isDebugValue() && "not a DBG_VALUE"); 43 Ranges.back().first->isIdenticalTo(&MI)) { 45 << "\t" << Ranges.back().first << "\t" << MI << "\ local 36 startInstrRange(InlinedVariable Var, const MachineInstr &MI) argument 51 endInstrRange(InlinedVariable Var, const MachineInstr &MI) argument 134 applyToClobberedRegisters(const MachineInstr &MI, const TargetRegisterInfo *TRI, Callable Func) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | Thumb2ITBlockPass.cpp | 44 bool MoveCopyOutOfITBlock(MachineInstr *MI, 56 static void TrackDefUses(MachineInstr *MI, argument 63 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 64 MachineOperand &MO = MI->getOperand(i); 96 static void ClearKillFlags(MachineInstr *MI, SmallSet<unsigned, 4> &Uses) { argument 97 for (MachineOperand &MO : MI->operands()) { 106 static bool isCopy(MachineInstr *MI) { argument 107 switch (MI->getOpcode()) { 119 Thumb2ITBlockPass::MoveCopyOutOfITBlock(MachineInstr *MI, argument 123 if (!isCopy(MI)) 182 MachineInstr *MI = &*MBBI; local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | OptimizePHIs.cpp | 53 bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg, 55 bool IsDeadPHICycle(MachineInstr *MI, InstrSet &PHIsInCycle); 83 /// IsSingleValuePHICycle - Check if MI is a PHI where all the source operands 88 bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI, argument 91 assert(MI->isPHI() && "IsSingleValuePHICycle expects a PHI instruction"); 92 unsigned DstReg = MI->getOperand(0).getReg(); 95 if (!PHIsInCycle.insert(MI).second) 103 for (unsigned i = 1; i != MI->getNumOperands(); i += 2) { 104 unsigned SrcReg = MI->getOperand(i).getReg(); 133 bool OptimizePHIs::IsDeadPHICycle(MachineInstr *MI, InstrSe argument 161 MachineInstr *MI = &*MII++; local [all...] |
H A D | ProcessImplicitDefs.cpp | 35 void processImplicitDef(MachineInstr *MI); 36 bool canTurnIntoImplicitDef(MachineInstr *MI); 65 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) { argument 66 if (!MI->isCopyLike() && 67 !MI->isInsertSubreg() && 68 !MI->isRegSequence() && 69 !MI->isPHI()) 71 for (const MachineOperand &MO : MI->operands()) 77 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { argument 78 DEBUG(dbgs() << "Processing " << *MI); [all...] |
H A D | MachineCSE.cpp | 83 bool PerformTrivialCopyPropagation(MachineInstr *MI, 88 bool hasLivePhysRegDefUses(const MachineInstr *MI, 93 bool PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, 97 bool isCSECandidate(MachineInstr *MI); 99 MachineInstr *CSMI, MachineInstr *MI); 122 bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI, argument 125 for (MachineOperand &MO : MI->operands()) { 158 DEBUG(dbgs() << "*** to: " << *MI); 159 // Propagate SrcReg of copies to MI. 215 bool MachineCSE::hasLivePhysRegDefUses(const MachineInstr *MI, argument 265 PhysRegDefsReach(MachineInstr *CSMI, MachineInstr *MI, SmallSet<unsigned,8> &PhysRefs, SmallVectorImpl<unsigned> &PhysDefs, bool &NonLocal) const argument 331 isCSECandidate(MachineInstr *MI) argument 360 isProfitableToCSE(unsigned CSReg, unsigned Reg, MachineInstr *CSMI, MachineInstr *MI) argument 451 MachineInstr *MI = &*I; local [all...] |
H A D | PeepholeOptimizer.cpp | 151 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB); 152 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB, 154 bool optimizeSelect(MachineInstr *MI, 156 bool optimizeCondBranch(MachineInstr *MI); 157 bool optimizeCoalescableCopy(MachineInstr *MI); 158 bool optimizeUncoalescableCopy(MachineInstr *MI, 162 bool isMoveImmediate(MachineInstr *MI, 165 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB, 169 /// \brief If copy instruction \p MI is a virtual register copy, track it in 173 bool foldRedundantCopy(MachineInstr *MI, 194 isCoalescableCopy(const MachineInstr &MI) argument 204 isUncoalescableCopy(const MachineInstr &MI) argument 561 optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB) argument 582 optimizeSelect(MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) argument 601 optimizeCondBranch(MachineInstr *MI) argument 749 CopyRewriter(MachineInstr &MI) argument 889 UncoalescableRewriter(MachineInstr &MI, const TargetInstrInfo &TII, MachineRegisterInfo &MRI) argument 967 InsertSubregRewriter(MachineInstr &MI) argument 1020 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII) argument 1082 RegSequenceRewriter(MachineInstr &MI) argument 1149 getCopyRewriter(MachineInstr &MI, const TargetInstrInfo &TII, MachineRegisterInfo &MRI) argument 1184 optimizeCoalescableCopy(MachineInstr *MI) argument 1245 optimizeUncoalescableCopy( MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) argument 1295 isLoadFoldable( MachineInstr *MI, SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) argument 1316 isMoveImmediate( MachineInstr *MI, SmallSet<unsigned, 4> &ImmDefRegs, DenseMap<unsigned, MachineInstr *> &ImmDefMIs) argument 1337 foldImmediate( MachineInstr *MI, MachineBasicBlock *MBB, SmallSet<unsigned, 4> &ImmDefRegs, DenseMap<unsigned, MachineInstr *> &ImmDefMIs) argument 1376 foldRedundantCopy( MachineInstr *MI, SmallSet<unsigned, 4> &CopySrcRegs, DenseMap<unsigned, MachineInstr *> &CopyMIs) argument 1425 foldRedundantNAPhysCopy( MachineInstr *MI, DenseMap<unsigned, MachineInstr *> &NAPhysToVirtMIs) argument 1517 MachineInstr *MI = &*MII; local [all...] |
H A D | RegAllocFast.cpp | 165 void handleThroughOperands(MachineInstr *MI, 173 void spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator); 174 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg); 177 void definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState); 187 LiveRegMap::iterator allocVirtReg(MachineInstr *MI, LiveRegMap::iterator, 189 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum, 191 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum, 193 void spillAll(MachineBasicBlock::iterator MI); 194 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg); 266 void RAFast::spillVirtReg(MachineBasicBlock::iterator MI, unsigne argument 275 spillVirtReg(MachineBasicBlock::iterator MI, LiveRegMap::iterator LRI) argument 328 spillAll(MachineBasicBlock::iterator MI) argument 407 definePhysReg(MachineInstr *MI, unsigned PhysReg, RegState NewState) argument 515 allocVirtReg(MachineInstr *MI, LiveRegMap::iterator LRI, unsigned Hint) argument 590 defineVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument 623 reloadVirtReg(MachineInstr *MI, unsigned OpNum, unsigned VirtReg, unsigned Hint) argument 674 setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) argument 703 handleThroughOperands(MachineInstr *MI, SmallVectorImpl<unsigned> &VirtDead) argument 811 MachineInstr *MI = MII++; local [all...] |
H A D | LiveDebugValues.cpp | 71 const MachineInstr *MI; // MachineInstr should be a DBG_VALUE instr. member in struct:__anon2467::LiveDebugValues::VarLoc 73 VarLoc(DebugVariable _var, const MachineInstr *_mi) : Var(_var), MI(_mi) {} 81 void transferDebugValue(MachineInstr &MI, VarLocList &OpenRanges); 82 void transferRegisterDef(MachineInstr &MI, VarLocList &OpenRanges); 83 bool transferTerminatorInst(MachineInstr &MI, VarLocList &OpenRanges, 85 bool transfer(MachineInstr &MI, VarLocList &OpenRanges, VarLocInMBB &OutLocs); 130 // \brief If @MI is a DBG_VALUE with debug value described by a defined 132 static unsigned isDescribedByReg(const MachineInstr &MI) { argument 133 assert(MI.isDebugValue()); 134 assert(MI 185 transferDebugValue(MachineInstr &MI, VarLocList &OpenRanges) argument 209 transferRegisterDef(MachineInstr &MI, VarLocList &OpenRanges) argument 227 transferTerminatorInst(MachineInstr &MI, VarLocList &OpenRanges, VarLocInMBB &OutLocs) argument 255 transfer(MachineInstr &MI, VarLocList &OpenRanges, VarLocInMBB &OutLocs) argument 312 MachineInstr *MI = local [all...] |
H A D | DeadMachineInstructionElim.cpp | 46 bool isDead(const MachineInstr *MI) const; 55 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { 59 if (MI->isInlineAsm()) 63 if (MI->getOpcode() == TargetOpcode::LOCAL_ESCAPE) 68 if (!MI->isSafeToMove(nullptr, SawStore) && !MI->isPHI()) 72 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 73 const MachineOperand &MO = MI->getOperand(i); 120 MachineInstr *MI = &*MII; local 123 if (isDead(MI)) { [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonNewValueJump.cpp | 95 bool isNewValueJumpCandidate(const MachineInstr *MI) const; 137 // feeder insn between it's definition, this MI and jump, jmpInst 222 MachineInstr *MI = II; local 227 int64_t v = MI->getOperand(2).getImm(); 230 ((MI->getOpcode() == Hexagon::C2_cmpeqi || 231 MI->getOpcode() == Hexagon::C2_cmpgti) && 237 cmpReg1 = MI->getOperand(1).getReg(); 240 cmpOp2 = MI->getOperand(2).getReg(); 286 // Make sure that MI here is included in isNewValueJumpCandidate. 287 static unsigned getNewValueJumpOpcode(MachineInstr *MI, in argument 438 MachineInstr *MI = --MII; local [all...] |
H A D | HexagonAsmPrinter.h | 43 void EmitInstruction(const MachineInstr *MI) override; 49 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); 50 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, 53 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCTOCRegDeps.cpp | 102 bool hasTOCLoReloc(const MachineInstr &MI) { argument 103 if (MI.getOpcode() == PPC::LDtocL || 104 MI.getOpcode() == PPC::ADDItocL) 107 for (const MachineOperand &MO : MI.operands()) { 118 for (auto &MI : MBB) { 119 if (!hasTOCLoReloc(MI)) 122 MI.addOperand(MachineOperand::CreateReg(PPC::X2,
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 110 MachineInstr &MI, 119 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false); 120 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 133 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) 138 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1) 141 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false); 142 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset)); 151 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1) 153 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1) 156 BuildMI(*MI 108 replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II, MachineInstr &MI, DebugLoc dl, unsigned FIOperandNum, int Offset, unsigned FramePtr) argument 170 MachineInstr &MI = *II; local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 122 inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) { argument 123 if (MI->getOperand(Op).isFI()) return true; 124 return Op+X86::AddrSegmentReg <= MI->getNumOperands() && 125 MI->getOperand(Op+X86::AddrBaseReg).isReg() && 126 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) && 127 MI->getOperand(Op+X86::AddrIndexReg).isReg() && 128 (MI->getOperand(Op+X86::AddrDisp).isImm() || 129 MI->getOperand(Op+X86::AddrDisp).isGlobal() || 130 MI->getOperand(Op+X86::AddrDisp).isCPI() || 131 MI 134 isMem(const MachineInstr *MI, unsigned Op) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/BPF/InstPrinter/ |
H A D | BPFInstPrinter.cpp | 29 void BPFInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 31 printInstruction(MI, O); 52 void BPFInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, argument 55 const MCOperand &Op = MI->getOperand(OpNo); 66 void BPFInstPrinter::printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O, argument 68 const MCOperand &RegOp = MI->getOperand(OpNo); 69 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1); 81 void BPFInstPrinter::printImm64Operand(const MCInst *MI, unsigned OpNo, argument 83 const MCOperand &Op = MI->getOperand(OpNo);
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | AMDGPUMCCodeEmitter.h | 31 uint64_t getBinaryCodeForInstr(const MCInst &MI, 35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, argument 41 virtual unsigned getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | R600Packetizer.cpp | 66 unsigned getSlot(const MachineInstr *MI) const { 67 return TRI.getHWRegChan(MI->getOperand(0).getReg()); 132 void substitutePV(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PVs) argument 140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); 143 unsigned Src = MI->getOperand(OperandIdx).getReg(); 146 MI->getOperand(OperandIdx).setReg(It->second); 165 bool ignorePseudoInstruction(const MachineInstr *MI, 170 // isSoloInstruction - return true if instruction MI can not be packetized 171 // with any other instruction, which means that MI itself is a packet. 172 bool isSoloInstruction(const MachineInstr *MI) overrid 229 setIsLastBit(MachineInstr *MI, unsigned Bit) const argument 234 isBundlableWithCurrentPMI(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, std::vector<R600InstrInfo::BankSwizzle> &BS, bool &isTransSlot) argument 306 MachineInstr *MI = CurrentPacketMIs[i]; variable 353 MachineBasicBlock::iterator MI = MBB->begin(); local [all...] |
H A D | R600InstrInfo.h | 37 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const; 65 MachineBasicBlock::iterator MI, DebugLoc DL, 71 bool isTrig(const MachineInstr &MI) const; 85 bool canBeConsideredALU(const MachineInstr *MI) const; 88 bool isTransOnly(const MachineInstr *MI) const; 90 bool isVectorOnly(const MachineInstr *MI) const; 94 bool usesVertexCache(const MachineInstr *MI) const; 96 bool usesTextureCache(const MachineInstr *MI) const; 99 bool usesAddressRegister(MachineInstr *MI) const; 100 bool definesAddressRegister(MachineInstr *MI) cons [all...] |
H A D | R600ClauseMergePass.cpp | 34 static bool isCFAlu(const MachineInstr *MI) { argument 35 switch (MI->getOpcode()) { 50 unsigned getCFAluSize(const MachineInstr *MI) const; 51 bool isCFAluEnabled(const MachineInstr *MI) const; 74 unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr *MI) const { 75 assert(isCFAlu(MI)); 76 return MI->getOperand( 77 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm(); 80 bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr *MI) const { 81 assert(isCFAlu(MI)); 178 MachineInstr *MI = I++; local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsSEISelLowering.h | 43 EmitInstrWithCustomInserter(MachineInstr *MI, 80 MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, 82 MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI, 86 MachineBasicBlock *emitCOPY_FW(MachineInstr *MI, 89 MachineBasicBlock *emitCOPY_FD(MachineInstr *MI, 92 MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, 95 MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, 98 MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI, 103 MachineBasicBlock *emitFILL_FW(MachineInstr *MI, 106 MachineBasicBlock *emitFILL_FD(MachineInstr *MI, [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCCodeEmitter.cpp | 44 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 50 uint64_t getBinaryCodeForInstr(const MCInst &MI, 56 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 60 unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 63 unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, 66 unsigned getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, 69 unsigned getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, 82 void SparcMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, argument 85 unsigned Bits = getBinaryCodeForInstr(MI, Fixups, STI); 95 switch (MI 115 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 142 getCallTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 177 getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 190 getBranchPredTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 202 getBranchOnRegTargetOpValue(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/ |
H A D | MachineInstrBuilder.h | 47 MachineInstr *MI; member in class:llvm::MachineInstrBuilder 49 MachineInstrBuilder() : MF(nullptr), MI(nullptr) {} 53 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {} 56 operator MachineInstr*() const { return MI; } 57 MachineInstr *operator->() const { return MI; } 58 operator MachineBasicBlock::iterator() const { return MI; } 62 MachineInstr *getInstr() const { return MI; } 69 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo, 84 MI->addOperand(*MF, MachineOperand::CreateImm(Val)); 89 MI 263 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 274 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 301 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 311 MachineInstr *MI = MF.CreateMachineInstr(MCID, DL); local 386 MachineInstr *MI = local 441 MachineInstr *MI = B; local 449 MIBundleBuilder(MachineInstr *MI) argument 467 insert(MachineBasicBlock::instr_iterator I, MachineInstr *MI) argument 489 prepend(MachineInstr *MI) argument 495 append(MachineInstr *MI) argument [all...] |
H A D | StackMaps.h | 27 /// \brief MI-level patchpoint operands. 29 /// MI patchpoint operations take the form: 47 const MachineInstr *MI; member in class:llvm::PatchPointOpers 52 explicit PatchPointOpers(const MachineInstr *MI); 63 return MI->getOperand(getMetaIdx(Pos)); 72 MI->getOperand(getMetaIdx(NArgPos)).getImm(); 87 /// MI-level Statepoint operands 106 explicit StatepointOpers(const MachineInstr *MI) : MI(MI) {} argument 128 const MachineInstr *MI; member in class:llvm::StatepointOpers [all...] |