1249259Sdim//===-- MipsSEISelLowering.h - MipsSE DAG Lowering Interface ----*- C++ -*-===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// Subclass of MipsTargetLowering specialized for mips32/64. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14280031Sdim#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 15280031Sdim#define LLVM_LIB_TARGET_MIPS_MIPSSEISELLOWERING_H 16249259Sdim 17249259Sdim#include "MipsISelLowering.h" 18249259Sdim#include "MipsRegisterInfo.h" 19249259Sdim 20249259Sdimnamespace llvm { 21249259Sdim class MipsSETargetLowering : public MipsTargetLowering { 22249259Sdim public: 23280031Sdim explicit MipsSETargetLowering(const MipsTargetMachine &TM, 24276479Sdim const MipsSubtarget &STI); 25249259Sdim 26261991Sdim /// \brief Enable MSA support for the given integer type and Register 27261991Sdim /// class. 28261991Sdim void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC); 29261991Sdim /// \brief Enable MSA support for the given floating-point type and 30261991Sdim /// Register class. 31261991Sdim void addMSAFloatType(MVT::SimpleValueType Ty, 32261991Sdim const TargetRegisterClass *RC); 33261991Sdim 34280031Sdim bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS = 0, 35280031Sdim unsigned Align = 1, 36280031Sdim bool *Fast = nullptr) const override; 37249259Sdim 38276479Sdim SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 39249259Sdim 40276479Sdim SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 41249259Sdim 42276479Sdim MachineBasicBlock * 43276479Sdim EmitInstrWithCustomInserter(MachineInstr *MI, 44276479Sdim MachineBasicBlock *MBB) const override; 45249259Sdim 46276479Sdim bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 47276479Sdim EVT VT) const override { 48251662Sdim return false; 49251662Sdim } 50251662Sdim 51276479Sdim const TargetRegisterClass *getRepRegClassFor(MVT VT) const override; 52249259Sdim 53249259Sdim private: 54277320Sdim bool isEligibleForTailCallOptimization( 55277320Sdim const CCState &CCInfo, unsigned NextStackOffset, 56277320Sdim const MipsFunctionInfo &FI) const override; 57249259Sdim 58276479Sdim void 59249259Sdim getOpndList(SmallVectorImpl<SDValue> &Ops, 60249259Sdim std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 61249259Sdim bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 62280031Sdim bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee, 63276479Sdim SDValue Chain) const override; 64249259Sdim 65261991Sdim SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const; 66261991Sdim SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const; 67261991Sdim 68249259Sdim SDValue lowerMulDiv(SDValue Op, unsigned NewOpc, bool HasLo, bool HasHi, 69249259Sdim SelectionDAG &DAG) const; 70249259Sdim 71251662Sdim SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const; 72251662Sdim SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const; 73261991Sdim SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const; 74261991Sdim SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 75261991Sdim SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 76261991Sdim /// \brief Lower VECTOR_SHUFFLE into one of a number of instructions 77261991Sdim /// depending on the indices in the shuffle. 78261991Sdim SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const; 79251662Sdim 80249259Sdim MachineBasicBlock *emitBPOSGE32(MachineInstr *MI, 81249259Sdim MachineBasicBlock *BB) const; 82261991Sdim MachineBasicBlock *emitMSACBranchPseudo(MachineInstr *MI, 83261991Sdim MachineBasicBlock *BB, 84261991Sdim unsigned BranchOp) const; 85261991Sdim /// \brief Emit the COPY_FW pseudo instruction 86261991Sdim MachineBasicBlock *emitCOPY_FW(MachineInstr *MI, 87261991Sdim MachineBasicBlock *BB) const; 88261991Sdim /// \brief Emit the COPY_FD pseudo instruction 89261991Sdim MachineBasicBlock *emitCOPY_FD(MachineInstr *MI, 90261991Sdim MachineBasicBlock *BB) const; 91261991Sdim /// \brief Emit the INSERT_FW pseudo instruction 92261991Sdim MachineBasicBlock *emitINSERT_FW(MachineInstr *MI, 93261991Sdim MachineBasicBlock *BB) const; 94261991Sdim /// \brief Emit the INSERT_FD pseudo instruction 95261991Sdim MachineBasicBlock *emitINSERT_FD(MachineInstr *MI, 96261991Sdim MachineBasicBlock *BB) const; 97276479Sdim /// \brief Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction 98276479Sdim MachineBasicBlock *emitINSERT_DF_VIDX(MachineInstr *MI, 99276479Sdim MachineBasicBlock *BB, 100276479Sdim unsigned EltSizeInBytes, 101276479Sdim bool IsFP) const; 102261991Sdim /// \brief Emit the FILL_FW pseudo instruction 103261991Sdim MachineBasicBlock *emitFILL_FW(MachineInstr *MI, 104261991Sdim MachineBasicBlock *BB) const; 105261991Sdim /// \brief Emit the FILL_FD pseudo instruction 106261991Sdim MachineBasicBlock *emitFILL_FD(MachineInstr *MI, 107261991Sdim MachineBasicBlock *BB) const; 108261991Sdim /// \brief Emit the FEXP2_W_1 pseudo instructions. 109261991Sdim MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI, 110261991Sdim MachineBasicBlock *BB) const; 111261991Sdim /// \brief Emit the FEXP2_D_1 pseudo instructions. 112261991Sdim MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, 113261991Sdim MachineBasicBlock *BB) const; 114249259Sdim }; 115249259Sdim} 116249259Sdim 117280031Sdim#endif 118