Lines Matching refs:MI
34 static bool isCFAlu(const MachineInstr *MI) {
35 switch (MI->getOpcode()) {
50 unsigned getCFAluSize(const MachineInstr *MI) const;
51 bool isCFAluEnabled(const MachineInstr *MI) const;
74 unsigned R600ClauseMergePass::getCFAluSize(const MachineInstr *MI) const {
75 assert(isCFAlu(MI));
76 return MI->getOperand(
77 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::COUNT)).getImm();
80 bool R600ClauseMergePass::isCFAluEnabled(const MachineInstr *MI) const {
81 assert(isCFAlu(MI));
82 return MI->getOperand(
83 TII->getOperandIdx(MI->getOpcode(), AMDGPU::OpName::Enabled)).getImm();
96 MachineInstr *MI = I++;
97 if (isCFAluEnabled(MI))
99 CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
100 MI->eraseFromParent();
178 MachineInstr *MI = I++;
179 if ((!TII->canBeConsideredALU(MI) && !isCFAlu(MI)) ||
180 TII->mustBeLastInClause(MI->getOpcode()))
182 if (!isCFAlu(MI))
184 cleanPotentialDisabledCFAlu(MI);
186 if (LatestCFAlu != E && mergeIfPossible(LatestCFAlu, MI)) {
187 MI->eraseFromParent();
189 assert(MI->getOperand(8).getImm() && "CF ALU instruction disabled");
190 LatestCFAlu = MI;