Searched refs:MI (Results 301 - 325 of 562) sorted by relevance

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/freebsd-11.0-release/contrib/llvm/tools/lldb/tools/lldb-mi/
H A DMICmdFactory.h24 // Details: MI Command Factory. Holds a list of registered MI commands that
25 // MI application understands to interpret. Creates commands objects.
29 class CMICmdFactory : public CMICmnBase, public MI::ISingleton<CMICmdFactory>
31 friend class MI::ISingleton<CMICmdFactory>;
H A DMICmdInvoker.h26 // Details: MI Command Invoker. The Invoker works on the command pattern design.
31 // back a MI result. In the meantime the Command Monitor is monitoring
40 class CMICmdInvoker : public CMICmnBase, public CMICmdMgrSetCmdDeleteCallback::ICallback, public MI::ISingleton<CMICmdInvoker>
42 friend class MI::ISingleton<CMICmdInvoker>;
H A DMICmnLog.h21 // Details: MI common code implementation class. Handle application trace
30 class CMICmnLog : public MI::ISingleton<CMICmnLog>
32 friend MI::ISingleton<CMICmnLog>;
45 eLogVerbosity_ClientMsg = 0x00000010, // A client using MI can insert messages into the log (not implemented)
84 // MI common object handling - duplicate of CMICmnBase functions, necessary for LINUX build
92 // From MI::ISingleton
124 // MI common object handling - duplicate of CMICmnBase functions, necessary for LINUX build
H A DMICmnThreadMgrStd.h22 // Details: MI's worker thread (active thread) manager.
29 class CMICmnThreadMgrStd : public CMICmnBase, public MI::ISingleton<CMICmnThreadMgrStd>
31 friend MI::ISingleton<CMICmnThreadMgrStd>;
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp76 MachineInstr *MI = MO.getParent(); local
77 unsigned OpNo = &MO - &MI->getOperand(0);
78 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
127 MachineInstr *MI = MO->getParent(); local
128 if (!MI) {
135 MachineOperand *MO0 = &MI->getOperand(0);
136 unsigned NumOps = MI->getNumOperands();
140 << " doesn't belong to parent MI: " << *MI; local
445 static const Function *getCalledFunction(const MachineInstr &MI) { argument
458 const MachineInstr &MI = *MO.getParent(); local
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H A DLivePhysRegs.cpp44 void LivePhysRegs::stepBackward(const MachineInstr &MI) { argument
46 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
59 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
73 void LivePhysRegs::stepForward(const MachineInstr &MI, argument
76 for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) {
H A DMachineTraceMetrics.cpp99 for (const auto &MI : *MBB) {
100 if (MI.isTransient())
103 if (MI.isCall())
109 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
598 // A data dependency is represented as a defining MI and operand numbers on the
599 // defining and using MI.
679 const MachineInstr *MI;
684 LiveRegUnit(unsigned RU) : RegUnit(RU), Cycle(0), MI(nullptr), Op(0) {}
697 for (MachineInstr::const_mop_iterator MI = UseMI->operands_begin(),
698 ME = UseMI->operands_end(); MI !
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H A DRegisterPressure.cpp332 void collectInstr(const MachineInstr &MI) const {
333 for (ConstMIBundleOperands OperI(&MI); OperI.isValid(); ++OperI)
378 void RegisterOperands::collect(const MachineInstr &MI, argument
383 Collector.collectInstr(MI);
386 void RegisterOperands::detectDeadDefs(const MachineInstr &MI, argument
388 SlotIndex SlotIdx = LIS.getInstructionIndex(&MI);
575 const MachineInstr &MI = *CurrPos; local
577 RegOpers.collect(MI, *TRI, *MRI);
579 RegOpers.detectDeadDefs(MI, *LIS);
728 void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) { argument
764 getMaxUpwardPressureDelta(const MachineInstr *MI, PressureDiff *PDiff, RegPressureDelta &Delta, ArrayRef<PressureChange> CriticalPSets, ArrayRef<unsigned> MaxPressureLimit) argument
832 getUpwardPressureDelta(const MachineInstr *MI, PressureDiff &PDiff, RegPressureDelta &Delta, ArrayRef<PressureChange> CriticalPSets, ArrayRef<unsigned> MaxPressureLimit) const argument
908 bumpDownwardPressure(const MachineInstr *MI) argument
958 getMaxDownwardPressureDelta(const MachineInstr *MI, RegPressureDelta &Delta, ArrayRef<PressureChange> CriticalPSets, ArrayRef<unsigned> MaxPressureLimit) argument
981 getUpwardPressure(const MachineInstr *MI, std::vector<unsigned> &PressureResult, std::vector<unsigned> &MaxPressureResult) argument
997 getDownwardPressure(const MachineInstr *MI, std::vector<unsigned> &PressureResult, std::vector<unsigned> &MaxPressureResult) argument
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H A DShrinkWrap.cpp132 /// \brief Check if \p MI uses or defines a callee-saved register or
133 /// a frame index. If this is the case, this means \p MI must happen
135 bool useOrDefCSROrFI(const MachineInstr &MI, RegScavenger *RS) const;
223 bool ShrinkWrap::useOrDefCSROrFI(const MachineInstr &MI, argument
225 if (MI.getOpcode() == FrameSetupOpcode ||
226 MI.getOpcode() == FrameDestroyOpcode) {
227 DEBUG(dbgs() << "Frame instruction: " << MI << '\n');
230 for (const MachineOperand &MO : MI.operands()) {
250 << MO.isFI() << "): " << MI << '\n');
455 for (const MachineInstr &MI
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H A DLiveRangeCalc.cpp45 const MachineInstr *MI = MO.getParent(); local
47 Indexes.getInstructionIndex(MI).getRegSlot(MO.isEarlyClobber());
168 const MachineInstr *MI = MO.getParent(); local
169 unsigned OpNo = (&MO - &MI->getOperand(0));
171 if (MI->isPHI()) {
175 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB());
182 else if (MI->isRegTiedToDefOperand(OpNo, &DefIdx)) {
185 isEarlyClobber = MI->getOperand(DefIdx).isEarlyClobber();
187 UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber);
190 // MI i
278 const MachineInstr *MI = Indexes->getInstructionFromIndex(Use); local
280 errs() << Use << " " << *MI; local
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H A DStackMapLivenessAnalysis.cpp73 void addLiveOutSetToMI(MachineFunction &MF, MachineInstr &MI);
148 MachineInstr &MI) {
151 MI.addOperand(MF, MO);
147 addLiveOutSetToMI(MachineFunction &MF, MachineInstr &MI) argument
H A DVirtRegMap.cpp331 const MachineInstr &MI = *MO.getParent(); local
332 SlotIndex BaseIndex = LIS->getInstructionIndex(&MI);
358 MachineInstr *MI = &*MII; local
361 for (MachineInstr::mop_iterator MOI = MI->operands_begin(),
362 MOE = MI->operands_end(); MOI != MOE; ++MOI) {
426 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true);
429 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true);
432 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI);
434 DEBUG(dbgs() << "> " << *MI);
437 if (MI
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H A DMIRPrinter.cpp113 void print(const MachineInstr &MI);
493 const MachineInstr &MI = *I; local
494 if (IsInBundle && !MI.isInsideBundle()) {
499 print(MI);
500 if (!IsInBundle && MI.getFlag(MachineInstr::BundledSucc)) {
512 static bool hasComplexRegisterTies(const MachineInstr &MI) { argument
513 const MCInstrDesc &MCID = MI.getDesc();
514 for (unsigned I = 0, E = MI.getNumOperands(); I < E; ++I) {
515 const auto &Operand = MI.getOperand(I);
520 int TiedIdx = Operand.isTied() ? int(MI
527 print(const MachineInstr &MI) argument
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H A DMachineBasicBlock.cpp136 void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) { argument
137 assert(!MI->getParent() && "MI is still in a block!");
138 Parent->getParent()->DeleteMachineInstr(MI);
146 "First non-phi MI cannot be inside a bundle!");
649 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
650 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
651 for (unsigned i = 2, e = MI
772 MachineInstr *MI = &*I; local
792 MachineInstr *MI = &*I; local
980 unbundleSingleMI(MachineInstr *MI) argument
997 remove_instr(MachineInstr *MI) argument
1005 insert(instr_iterator I, MachineInstr *MI) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h147 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
149 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
153 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
155 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
190 bool shouldCoalesce(MachineInstr *MI,
H A DARMMCInstLower.cpp118 void llvm::LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI, argument
120 OutMI.setOpcode(MI->getOpcode());
124 switch (MI->getOpcode()) {
150 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
151 const MachineOperand &MO = MI->getOperand(i);
H A DARMFrameLowering.cpp40 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
101 static bool isCSRestore(MachineInstr *MI, argument
105 if (isPopOpcode(MI->getOpcode())) {
108 for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
109 if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
113 if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
114 MI->getOpcode() == ARM::LDR_POST_REG ||
115 MI->getOpcode() == ARM::t2LDR_POST) &&
116 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
117 MI
148 sizeOfSPAdjustment(const MachineInstr *MI) argument
888 emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned StmOpc, unsigned StrOpc, bool NoGap, bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs, unsigned MIFlags) const argument
962 emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, unsigned LdmOpc, unsigned LdrOpc, bool isVarArg, bool NoGap, bool(*Func)(unsigned, bool), unsigned NumAlignedDPRCS2Regs) const argument
1064 emitAlignedDPRCS2Spills(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument
1196 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs) argument
1224 emitAlignedDPRCS2Restores(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned NumAlignedDPRCS2Regs, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) argument
1303 spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
1334 restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/Disassembler/
H A DSparcDisassembler.cpp262 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
313 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
316 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address, argument
333 status = DecodeRD(MI, rd, Address, Decoder);
339 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
345 MI.addOperand(MCOperand::createImm(simm13));
347 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
353 MI.addOperand(MCOperand::createImm(asi));
356 status = DecodeRD(MI, rd, Address, Decoder);
425 uint64_t Width, MCInst &MI,
423 tryAddingSymbolicOperand(int64_t Value, bool isBranch, uint64_t Address, uint64_t Offset, uint64_t Width, MCInst &MI, const void *Decoder) argument
432 DecodeCall(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
442 DecodeSIMM13(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
449 DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
483 DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
511 DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address, const void *Decoder) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp328 MachineInstr *MI = SU->getInstr(); local
330 if (MI->isDebugValue())
333 unsigned Opcode = MI->getOpcode();
375 if (isLoad && NumStores && !MI->memoperands_empty()) {
376 MachineMemOperand *MO = *MI->memoperands_begin();
386 MachineInstr *MI = SU->getInstr(); local
388 if (MI->isDebugValue())
391 unsigned Opcode = MI->getOpcode();
402 if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
403 MachineMemOperand *MO = *MI
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/Lex/
H A DPPMacroExpansion.cpp171 MacroInfo *MI = nullptr; local
178 MI = DMD->getInfo();
194 if (MI && NewMI != MI &&
195 !MI->isIdenticalTo(*NewMI, *this, /*Syntactically=*/true))
199 MI = NewMI;
261 if (auto *MI = MM->getMacroInfo()) {
263 MI->dump();
276 MacroInfo *MI = PP.AllocateMacroInfo(SourceLocation()); local
277 MI
342 isTrivialSingleTokenExpansion(const MacroInfo *MI, const IdentifierInfo *MacroIdent, Preprocessor &PP) argument
421 MacroInfo *MI = M.getMacroInfo(); local
706 ReadFunctionLikeMacroArgs(Token &MacroName, MacroInfo *MI, SourceLocation &MacroEnd) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/
H A DAMDILCFGStructurizer.cpp246 static MachineBasicBlock *getTrueBranch(MachineInstr *MI);
247 static void setTrueBranch(MachineInstr *MI, MachineBasicBlock *MBB);
249 MachineInstr *MI);
250 static bool isCondBranch(MachineInstr *MI);
251 static bool isUncondBranch(MachineInstr *MI);
473 MachineInstr *MI = MBB->getParent() local
475 MBB->push_back(MI);
477 SHOWNEWINSTR(MI);
482 MachineInstr *MI = local
485 MBB->insert(MBB->begin(), MI);
578 getTrueBranch(MachineInstr *MI) argument
582 setTrueBranch(MachineInstr *MI, MachineBasicBlock *MBB) argument
588 getFalseBranch(MachineBasicBlock *MBB, MachineInstr *MI) argument
598 isCondBranch(MachineInstr *MI) argument
609 isUncondBranch(MachineInstr *MI) argument
635 MachineInstr *MI = &*It; local
646 MachineInstr *MI = &*It; local
670 MachineInstr *MI = &(*It); local
678 MachineInstr *MI = getReturnInstr(MBB); local
702 MachineInstr *MI = Func->CloneMachineInstr(It); local
1603 MachineInstr *MI = getLoopendBlockBranchInstr(ContingMBB); local
1772 MachineInstr *MI = getReturnInstr(MBB); local
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/freebsd-11.0-release/contrib/llvm/include/llvm/CodeGen/
H A DMachineBasicBlock.h168 bundle_iterator(IterTy MI) : MII(MI) {} argument
170 bundle_iterator(Ty &MI) : MII(MI) { argument
171 assert(!MI.isBundledWithPred() &&
172 "It's not legal to initialize bundle_iterator with a bundled MI");
174 bundle_iterator(Ty *MI) : MII(MI) { argument
175 assert((!MI || !MI
570 push_back(MachineInstr *MI) argument
589 insert(iterator I, MachineInstr *MI) argument
598 insertAfter(iterator I, MachineInstr *MI) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp71 static void ImposeStackOrdering(MachineInstr *MI) { argument
73 if (!MI->definesRegister(WebAssembly::EXPR_STACK))
74 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
79 if (!MI->readsRegister(WebAssembly::EXPR_STACK))
80 MI->addOperand(MachineOperand::CreateReg(WebAssembly::EXPR_STACK,
242 for (MachineInstr &MI : MBB) {
243 for (MachineOperand &MO : reverse(MI.explicit_operands())) {
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp234 const MachineInstr *MI = &I; local
235 if (MI->isCall())
237 unsigned Opc = MI->getOpcode();
246 for (const MachineOperand &MO : MI->operands()) {
456 for (auto MI : AdjustRegs) {
457 assert((MI->getOpcode() == Hexagon::ALLOCA) && "Expected alloca");
458 expandAlloca(MI, HII, SP, MaxCF);
459 MI->eraseFromParent();
919 MachineBasicBlock::iterator MI = MBB.begin();
927 DebugLoc DL = MI !
1005 MachineInstr &MI = *I; local
1091 MachineInstr *MI = MII; local
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/freebsd-11.0-release/contrib/llvm/lib/CodeGen/AsmPrinter/
H A DAsmPrinter.cpp227 GCModuleInfo *MI = getAnalysisIfAvailable<GCModuleInfo>(); local
228 assert(MI && "AsmPrinter didn't require GCModuleInfo?");
229 for (auto &I : *MI)
231 MP->beginAssembly(M, *MI, *this);
687 static void emitComments(const MachineInstr &MI, raw_ostream &CommentOS) { argument
688 const MachineFunction *MF = MI.getParent()->getParent();
699 if (TII->isLoadFromStackSlotPostFE(&MI, FI)) {
701 MMO = *MI.memoperands_begin();
704 } else if (TII->hasLoadFromStackSlot(&MI, MMO, FI)) {
707 } else if (TII->isStoreToStackSlotPostFE(&MI, F
736 emitKill(const MachineInstr *MI, AsmPrinter &AP) argument
755 emitDebugValueComment(const MachineInstr *MI, AsmPrinter &AP) argument
872 emitCFIInstruction(const MachineInstr &MI) argument
888 emitFrameAlloc(const MachineInstr &MI) argument
1244 GCModuleInfo *MI = getAnalysisIfAvailable<GCModuleInfo>(); local
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