Target/ARM/ARMFrameLowering.cpp

40 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
101 static bool isCSRestore(MachineInstr *MI,
105   if (isPopOpcode(MI->getOpcode())) {
108     for (int i = 5, e = MI->getNumOperands(); i != e; ++i)
109       if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs))
113   if ((MI->getOpcode() == ARM::LDR_POST_IMM ||
114        MI->getOpcode() == ARM::LDR_POST_REG ||
115        MI->getOpcode() == ARM::t2LDR_POST) &&
116       isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) &&
117       MI->getOperand(1).getReg() == ARM::SP)
148 static int sizeOfSPAdjustment(const MachineInstr *MI) {
150   switch (MI->getOpcode()) {
168   for (int i = MI->getNumOperands() - 1; i >= 4; --i)
889                                     MachineBasicBlock::iterator MI,
940         AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
945       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc),
957     if (MI != MBB.begin())
958       --MI;
963                                    MachineBasicBlock::iterator MI,
976   if (MBB.end() != MI) {
977     DL = MI->getDebugLoc();
978     unsigned RetOpcode = MI->getOpcode();
1025         AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1029       if (DeleteRet && MI != MBB.end()) {
1030         MIB.copyImplicitOps(&*MI);
1031         MI->eraseFromParent();
1033       MI = MIB;
1040         BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1056     if (MI != MBB.end())
1057       ++MI;
1065                                     MachineBasicBlock::iterator MI,
1071   DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1111   AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1121   emitAligningInstructions(MF, AFI, TII, MBB, MI, DL, ARM::R4, MaxAlign, true);
1128   MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1144     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed),
1162     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Q))
1174     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VST1q64))
1184     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VSTRD))
1190   std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1196 skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI,
1201   ++MI; ++MI; ++MI;
1202   assert(MI->mayStore() && "Expecting spill instruction");
1207     ++MI;
1208     assert(MI->mayStore() && "Expecting spill instruction");
1210     ++MI;
1211     assert(MI->mayStore() && "Expecting spill instruction");
1215     assert(MI->killsRegister(ARM::R4) && "Missed kill flag");
1216     ++MI;
1218   return MI;
1225                                       MachineBasicBlock::iterator MI,
1231   DebugLoc DL = MI != MBB.end() ? MI->getDebugLoc() : DebugLoc();
1251   AddDefaultCC(AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1261     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1277     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1288     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1296     AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1300   std::prev(MI)->addRegisterKilled(ARM::R4, TRI);
1304                                         MachineBasicBlock::iterator MI,
1318   emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register, 0,
1320   emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register, 0,
1322   emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register,
1329     emitAlignedDPRCS2Spills(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1335                                         MachineBasicBlock::iterator MI,
1349     emitAlignedDPRCS2Restores(MBB, MI, NumAlignedDPRCS2Regs, CSI, TRI);
1354   emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register,
1356   emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1358   emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false,
1369     for (auto &MI : MBB)
1370       FnSize += TII.GetInstSizeInBytes(&MI);
1384     for (auto &MI : MBB) {
1385       for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
1386         if (!MI.getOperand(i).isFI())
1391         if (MI.getOpcode() == ARM::ADDri) {
1397         switch (MI.getDesc().TSFlags & ARMII::AddrModeMask) {