/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMOptimizeBarriersPass.cpp | 38 // The current implementation allows this iif MI does not have any possible 40 static bool CanMovePastDMB(const MachineInstr *MI) { argument 41 return !(MI->mayLoad() || 42 MI->mayStore() || 43 MI->hasUnmodeledSideEffects() || 44 MI->isCall() || 45 MI->isReturn()); 61 for (auto &MI : MBB) { 62 if (MI.getOpcode() == ARM::DMB) { 66 if (MI [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZShortenInst.cpp | 40 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH); 41 bool shortenOn0(MachineInstr &MI, unsigned Opcode); 42 bool shortenOn01(MachineInstr &MI, unsigned Opcode); 43 bool shortenOn001(MachineInstr &MI, unsigned Opcode); 44 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode); 45 bool shortenFPConv(MachineInstr &MI, unsigned Opcode); 62 // Tie operands if MI has become a two-address instruction. 63 static void tieOpsIfNeeded(MachineInstr &MI) { argument 64 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && 65 !MI 72 shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH) argument 103 shortenOn0(MachineInstr &MI, unsigned Opcode) argument 113 shortenOn01(MachineInstr &MI, unsigned Opcode) argument 125 shortenOn001(MachineInstr &MI, unsigned Opcode) argument 138 shortenOn001AddCC(MachineInstr &MI, unsigned Opcode) argument 152 shortenFPConv(MachineInstr &MI, unsigned Opcode) argument 184 MachineInstr &MI = *MBBI; local [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/InstPrinter/ |
H A D | X86ATTInstPrinter.h | 28 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, 33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS); 34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 38 void printInstruction(const MCInst *MI, raw_ostream &OS); 41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS); 42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); 43 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS); 44 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS); 45 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS); 46 void printSrcIdx(const MCInst *MI, unsigne 52 printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 56 printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 60 printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 63 printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 66 printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 69 printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 72 printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 75 printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 78 printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 81 printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 84 printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 87 printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 90 printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 93 printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 96 printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 100 printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 103 printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 106 printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 109 printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 112 printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 115 printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 118 printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 121 printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 124 printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 127 printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 130 printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 133 printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
H A D | X86IntelInstPrinter.h | 29 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot, 33 void printInstruction(const MCInst *MI, raw_ostream &O); 36 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 37 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O); 38 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O); 39 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O); 40 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O); 41 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O); 42 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O); 43 void printDstIdx(const MCInst *MI, unsigne 47 printanymem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 51 printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 56 printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 60 printi16mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 64 printi32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 68 printi64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 72 printi128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 76 printi256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 80 printi512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 84 printf32mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 88 printf64mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 92 printf80mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 96 printf128mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 100 printf256mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 104 printf512mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 110 printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 114 printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 118 printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 122 printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 126 printDstIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 130 printDstIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 134 printDstIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 138 printDstIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 142 printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 146 printMemOffs16(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 150 printMemOffs32(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 154 printMemOffs64(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
H A D | X86InstComments.cpp | 37 static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT, argument 39 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); 48 static void getZeroExtensionTypes(const MCInst *MI, MVT &SrcVT, MVT &DstVT) { argument 49 switch (MI->getOpcode()) { 180 static void getVSHUF64x2FamilyInfo(const MCInst *MI, MVT &VT, bool &HasMemOp) { argument 182 switch (MI->getOpcode()) { 189 VT = getRegOperandVectorVT(MI, MVT::i64, 0); 194 VT = getRegOperandVectorVT(MI, MVT::i32, 0); 206 bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, argument 212 switch (MI [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/InstPrinter/ |
H A D | AMDGPUInstPrinter.h | 27 void printInstruction(const MCInst *MI, raw_ostream &O); 30 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 36 void printU8ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 37 void printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 38 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 39 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 40 void printU32ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 41 void printOffen(const MCInst *MI, unsigned OpNo, raw_ostream &O); 42 void printIdxen(const MCInst *MI, unsigned OpNo, raw_ostream &O); 43 void printAddr64(const MCInst *MI, unsigne [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 46 unsigned isLoadFromStackSlot(const MachineInstr *MI, 54 unsigned isStoreToStackSlot(const MachineInstr *MI, 171 /// into real instructions. The target can edit MI in place, or it can insert 172 /// new instructions and erase MI. The function should return true if 174 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 183 MachineBasicBlock::iterator MI) const override; 186 bool isPredicated(const MachineInstr *MI) const override; 190 bool PredicateInstruction(MachineInstr *MI, 201 bool DefinesPredicate(MachineInstr *MI, 207 bool isPredicable(MachineInstr *MI) cons [all...] |
H A D | HexagonMachineFunctionInfo.h | 50 void addAllocaAdjustInst(MachineInstr* MI) { argument 51 AllocaAdjustInsts.push_back(MI); 60 void setStartPacket(MachineInstr* MI) { argument 61 PacketInfo[MI] |= Hexagon::StartPacket; 63 void setEndPacket(MachineInstr* MI) { argument 64 PacketInfo[MI] |= Hexagon::EndPacket; 66 bool isStartPacket(const MachineInstr* MI) const { 67 return (PacketInfo.count(MI) && 68 (PacketInfo.find(MI)->second & Hexagon::StartPacket)); 70 bool isEndPacket(const MachineInstr* MI) cons [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 32 static bool isReg(const MCInst &MI, unsigned OpNo) { argument 33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected."); 34 return MI.getOperand(OpNo).getReg() == R; 79 void MipsInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 81 switch (MI->getOpcode()) { 91 printSaveRestore(MI, O); 96 printSaveRestore(MI, O); 101 printSaveRestore(MI, O); 106 printSaveRestore(MI, O); 112 if (!printAliasInstr(MI, 189 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 206 printUnsignedImm(const MCInst *MI, int opNum, raw_ostream &O) argument 215 printUnsignedImm8(const MCInst *MI, int opNum, raw_ostream &O) argument 225 printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) argument 252 printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O) argument 262 printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) argument 268 printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) argument 273 printSHFMask(const MCInst *MI, int opNum, raw_ostream &O) argument 277 printAlias(const char *Str, const MCInst &MI, unsigned OpNo, raw_ostream &OS) argument 284 printAlias(const char *Str, const MCInst &MI, unsigned OpNo0, unsigned OpNo1, raw_ostream &OS) argument 293 printAlias(const MCInst &MI, raw_ostream &OS) argument 340 printSaveRestore(const MCInst *MI, raw_ostream &O) argument 351 printRegisterList(const MCInst *MI, int opNum, raw_ostream &O) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/CodeGen/ |
H A D | ExpandPostRAPseudos.cpp | 51 bool LowerSubregToReg(MachineInstr *MI); 52 bool LowerCopy(MachineInstr *MI); 54 void TransferImplicitDefs(MachineInstr *MI); 64 /// TransferImplicitDefs - MI is a pseudo-instruction, and the lowered 66 /// operands from MI to the replacement instruction. 68 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { argument 69 MachineBasicBlock::iterator CopyMI = MI; 72 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 73 MachineOperand &MO = MI->getOperand(i); 80 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { argument 137 LowerCopy(MachineInstr *MI) argument 195 MachineInstr *MI = mi; local [all...] |
H A D | AntiDepBreaker.h | 50 virtual void Observe(MachineInstr *MI, unsigned Count, 58 void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) { argument 59 assert (MI->isDebugValue() && "MI is not DBG_VALUE!"); 60 if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg) 61 MI->getOperand(0).setReg(NewReg);
|
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/InstPrinter/ |
H A D | SystemZInstPrinter.cpp | 52 void SystemZInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 55 printInstruction(MI, O); 64 static void printUImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { argument 65 int64_t Value = MI->getOperand(OpNum).getImm(); 71 static void printSImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) { argument 72 int64_t Value = MI->getOperand(OpNum).getImm(); 77 void SystemZInstPrinter::printU1ImmOperand(const MCInst *MI, int OpNum, argument 79 printUImmOperand<1>(MI, OpNum, O); 82 void SystemZInstPrinter::printU2ImmOperand(const MCInst *MI, int OpNum, argument 84 printUImmOperand<2>(MI, OpNu 87 printU3ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 92 printU4ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 97 printU6ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 102 printS8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 107 printU8ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 112 printU12ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 117 printS16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 122 printU16ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 127 printS32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 132 printU32ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument 137 printAccessRegOperand(const MCInst *MI, int OpNum, raw_ostream &O) argument [all...] |
H A D | SystemZInstPrinter.h | 29 void printInstruction(const MCInst *MI, raw_ostream &O); 42 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 47 void printOperand(const MCInst *MI, int OpNum, raw_ostream &O); 48 void printBDAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 49 void printBDXAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 50 void printBDLAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 51 void printBDVAddrOperand(const MCInst *MI, int OpNum, raw_ostream &O); 52 void printU1ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 53 void printU2ImmOperand(const MCInst *MI, int OpNum, raw_ostream &O); 54 void printU3ImmOperand(const MCInst *MI, in [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonInstPrinter.h | 30 void printInst(MCInst const *MI, raw_ostream &O, StringRef Annot, 33 void printInstruction(MCInst const *MI, raw_ostream &O); 39 void printOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const; 40 void printExtOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const; 41 void printUnsignedImmOperand(MCInst const *MI, unsigned OpNo, 43 void printNegImmOperand(MCInst const *MI, unsigned OpNo, 45 void printNOneImmOperand(MCInst const *MI, unsigned OpNo, 47 void prints3_6ImmOperand(MCInst const *MI, unsigned OpNo, 49 void prints3_7ImmOperand(MCInst const *MI, unsigned OpNo, 51 void prints4_6ImmOperand(MCInst const *MI, unsigne 69 printSymbolHi(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 72 printSymbolLo(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument [all...] |
H A D | HexagonInstPrinter.cpp | 53 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &OS, argument 55 assert(HexagonMCInstrInfo::isBundle(*MI)); 56 assert(HexagonMCInstrInfo::bundleSize(*MI) <= HEXAGON_PACKET_SIZE); 57 assert(HexagonMCInstrInfo::bundleSize(*MI) > 0); 59 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(*MI)) { 73 if (HexagonMCInstrInfo::isInnerLoop(*MI)) { 80 if (HexagonMCInstrInfo::isOuterLoop(*MI)) { 89 void HexagonInstPrinter::printOperand(MCInst const *MI, unsigned OpNo, argument 91 if (HexagonMCInstrInfo::getExtendableOp(MII, *MI) == OpNo && 92 (HasExtender || HexagonMCInstrInfo::isConstExtended(MII, *MI))) 108 printExtOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 113 printUnsignedImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 119 printNegImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 124 printNOneImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 129 prints3_6ImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 139 prints3_7ImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 149 prints4_6ImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 159 prints4_7ImmOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 169 printGlobalOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 174 printJumpTable(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 181 printConstantPool(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 188 printBranchOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 195 printCallOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 198 printAbsAddrOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 201 printPredicateOperand(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument 204 printSymbol(MCInst const *MI, unsigned OpNo, raw_ostream &O, bool hi) const argument 219 printBrtarget(MCInst const *MI, unsigned OpNo, raw_ostream &O) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | SILowerControlFlow.cpp | 78 void SkipIfDead(MachineInstr &MI); 80 void If(MachineInstr &MI); 81 void Else(MachineInstr &MI); 82 void Break(MachineInstr &MI); 83 void IfBreak(MachineInstr &MI); 84 void ElseBreak(MachineInstr &MI); 85 void Loop(MachineInstr &MI); 86 void EndCf(MachineInstr &MI); 88 void Kill(MachineInstr &MI); 89 void Branch(MachineInstr &MI); 150 SkipIfDead(MachineInstr &MI) argument 183 If(MachineInstr &MI) argument 201 Else(MachineInstr &MI) argument 220 Break(MachineInstr &MI) argument 234 IfBreak(MachineInstr &MI) argument 249 ElseBreak(MachineInstr &MI) argument 264 Loop(MachineInstr &MI) argument 279 EndCf(MachineInstr &MI) argument 292 Branch(MachineInstr &MI) argument 299 Kill(MachineInstr &MI) argument 328 LoadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset) argument 426 IndirectSrc(MachineInstr &MI) argument 446 IndirectDst(MachineInstr &MI) argument 486 MachineInstr &MI = *I; local [all...] |
H A D | SIInstrInfo.h | 29 unsigned buildExtractSubReg(MachineBasicBlock::iterator MI, 35 MachineOperand buildExtractSubRegOrImm(MachineBasicBlock::iterator MI, 68 unsigned findUsedSGPR(const MachineInstr *MI, int OpIndices[3]) const; 71 MachineInstr *commuteInstructionImpl(MachineInstr *MI, 83 bool isReallyTriviallyReMaterializable(const MachineInstr *MI, 99 MachineBasicBlock::iterator MI, DebugLoc DL, 104 MachineBasicBlock::iterator MI, 111 MachineBasicBlock::iterator MI, 117 MachineBasicBlock::iterator MI, 122 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) cons 154 isSALU(const MachineInstr &MI) argument 162 isVALU(const MachineInstr &MI) argument 170 isSOP1(const MachineInstr &MI) argument 178 isSOP2(const MachineInstr &MI) argument 186 isSOPC(const MachineInstr &MI) argument 194 isSOPK(const MachineInstr &MI) argument 202 isSOPP(const MachineInstr &MI) argument 210 isVOP1(const MachineInstr &MI) argument 218 isVOP2(const MachineInstr &MI) argument 226 isVOP3(const MachineInstr &MI) argument 234 isVOPC(const MachineInstr &MI) argument 242 isMUBUF(const MachineInstr &MI) argument 250 isMTBUF(const MachineInstr &MI) argument 258 isSMRD(const MachineInstr &MI) argument 266 isDS(const MachineInstr &MI) argument 274 isMIMG(const MachineInstr &MI) argument 282 isFLAT(const MachineInstr &MI) argument 290 isWQM(const MachineInstr &MI) argument 298 isVGPRSpill(const MachineInstr &MI) argument 360 getOpSize(const MachineInstr &MI, unsigned OpNo) const argument 452 getNamedOperand(const MachineInstr &MI, unsigned OpName) const argument 458 getNamedImmOperand(const MachineInstr &MI, unsigned OpName) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.h | 33 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 37 void printInstruction(const MCInst *MI, raw_ostream &O); 40 bool printAliasInstr(const MCInst *MI, raw_ostream &OS); 41 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 45 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 46 void printPredicateOperand(const MCInst *MI, unsigned OpNo, 49 void printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 50 void printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 51 void printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 52 void printU4ImmOperand(const MCInst *MI, unsigne [all...] |
H A D | PPCInstPrinter.cpp | 56 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 59 if (MI->getOpcode() == PPC::RLWINM) { 60 unsigned char SH = MI->getOperand(2).getImm(); 61 unsigned char MB = MI->getOperand(3).getImm(); 62 unsigned char ME = MI->getOperand(4).getImm(); 72 printOperand(MI, 0, O); 74 printOperand(MI, 1, O); 82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && 83 MI 156 printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O, const char *Modifier) argument 253 printU1ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 260 printU2ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 267 printU3ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 274 printU4ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 281 printS5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 288 printU5ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 295 printU6ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 302 printU10ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 309 printU12ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 316 printS16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 324 printU16ImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 332 printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 343 printAbsBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 352 printcrbitm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 370 printMemRegImm(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 381 printMemRegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 394 printTLSCall(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument 429 printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/InstPrinter/ |
H A D | AArch64InstPrinter.h | 27 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 32 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 34 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, 36 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, 47 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI, 50 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 52 void printHexImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 54 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm, 57 void printPostIncOperand(const MCInst *MI, unsigned OpNo, argument 59 printPostIncOperand(MI, OpN 84 printMemExtend(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 101 printUImm12Offset(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 107 printAMIndexedWB(const MCInst *MI, unsigned OpNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCCodeEmitter.cpp | 40 void encodeInstruction(const MCInst &MI, raw_ostream &OS, 46 uint64_t getBinaryCodeForInstr(const MCInst &MI, 51 // MO in MI. Fixups is the list of fixups against MI. 52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 60 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, 63 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, 66 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, 69 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, 72 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigne 89 getPC16DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 95 getPC32DBLEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 101 getPC16DBLTLSEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 107 getPC32DBLTLSEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 123 encodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 137 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 148 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 158 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 168 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 179 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 191 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 202 getBDVAddr12Encoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 213 getPCRelEncoding(const MCInst &MI, unsigned OpNum, SmallVectorImpl<MCFixup> &Fixups, unsigned Kind, int64_t Offset, bool AllowTLS) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/InstPrinter/ |
H A D | SparcInstPrinter.cpp | 46 void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O, argument 48 if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O)) 49 printInstruction(MI, STI, O); 53 bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, argument 56 switch (MI->getOpcode()) { 60 if (MI->getNumOperands() != 3) 62 if (!MI->getOperand(0).isReg()) 64 switch (MI->getOperand(0).getReg()) { 67 if (MI 107 printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 126 printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O, const char *Modifier) argument 149 printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument 173 printGetPCX(const MCInst *MI, unsigned opNum, const MCSubtargetInfo &STI, raw_ostream &O) argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/InstPrinter/ |
H A D | ARMInstPrinter.h | 26 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot, 31 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, 35 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, 38 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, 40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, 43 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, 45 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, 47 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, 49 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, 51 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigne [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCCodeEmitter.cpp | 51 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo, 54 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo, 57 unsigned getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, 60 unsigned getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, 63 unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo, 66 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo, 69 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo, 72 unsigned getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, 75 unsigned getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, 78 unsigned getSPE2DisEncoding(const MCInst &MI, unsigne 153 getDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 165 getCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 178 getAbsDirectBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 191 getAbsCondBrEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 203 getImm16Encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 215 getMemRIEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 234 getMemRIXEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 253 getSPE8DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 269 getSPE4DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 285 getSPE2DisEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 301 getTLSRegEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 317 getTLSCallEncoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 330 get_crbitm_encoding(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument 342 getMachineOpValue(const MCInst &MI, const MCOperand &MO, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCMIPeephole.cpp | 1 //===-------------- PPCMIPeephole.cpp - MI Peephole Cleanups -------------===// 76 DEBUG(dbgs() << "*** PowerPC MI peephole pass ***\n\n"); 86 for (MachineInstr &MI : MBB) { 96 if (MI.isDebugValue()) 100 switch (MI.getOpcode()) { 109 int Immed = MI.getOperand(3).getImm(); 119 unsigned TrueReg1 = lookThruCopyLike(MI.getOperand(1).getReg()); 120 unsigned TrueReg2 = lookThruCopyLike(MI.getOperand(2).getReg()); 139 DEBUG(MI.dump()); 140 BuildMI(MBB, &MI, M 201 MachineInstr *MI = MRI->getVRegDef(SrcReg); local [all...] |