Target/SystemZ/SystemZShortenInst.cpp

40   bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
41   bool shortenOn0(MachineInstr &MI, unsigned Opcode);
42   bool shortenOn01(MachineInstr &MI, unsigned Opcode);
43   bool shortenOn001(MachineInstr &MI, unsigned Opcode);
44   bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
45   bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
62 // Tie operands if MI has become a two-address instruction.
63 static void tieOpsIfNeeded(MachineInstr &MI) {
64   if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
65       !MI.getOperand(0).isTied())
66     MI.tieOperands(0, 1);
69 // MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
72 bool SystemZShortenInst::shortenIIF(MachineInstr &MI,
74   unsigned Reg = MI.getOperand(0).getReg();
87   uint64_t Imm = MI.getOperand(1).getImm();
89     MI.setDesc(TII->get(LLIxL));
90     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
94     MI.setDesc(TII->get(LLIxH));
95     MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
96     MI.getOperand(1).setImm(Imm >> 16);
102 // Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
103 bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
104   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
105     MI.setDesc(TII->get(Opcode));
111 // Change MI's opcode to Opcode if register operands 0 and 1 have a
113 bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
114   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
115       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
116     MI.setDesc(TII->get(Opcode));
122 // Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
124 // with op 1, if MI becomes 2-address.
125 bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
126   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
127       MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
128       SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
129     MI.setDesc(TII->get(Opcode));
130     tieOpsIfNeeded(MI);
138 bool SystemZShortenInst::shortenOn001AddCC(MachineInstr &MI,
140   if (!LiveRegs.contains(SystemZ::CC) && shortenOn001(MI, Opcode)) {
141     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
148 // MI is a vector-style conversion instruction with the operand order:
152 bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
153   if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
154       SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
155     MachineOperand Dest(MI.getOperand(0));
156     MachineOperand Src(MI.getOperand(1));
157     MachineOperand Suppress(MI.getOperand(2));
158     MachineOperand Mode(MI.getOperand(3));
159     MI.RemoveOperand(3);
160     MI.RemoveOperand(2);
161     MI.RemoveOperand(1);
162     MI.RemoveOperand(0);
163     MI.setDesc(TII->get(Opcode));
164     MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
184     MachineInstr &MI = *MBBI;
185     switch (MI.getOpcode()) {
187       Changed |= shortenIIF(MI, SystemZ::LLILL, SystemZ::LLILH);
191       Changed |= shortenIIF(MI, SystemZ::LLIHL, SystemZ::LLIHH);
195       Changed |= shortenOn001AddCC(MI, SystemZ::ADBR);
199       Changed |= shortenOn001(MI, SystemZ::DDBR);
203       Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
207       Changed |= shortenOn01(MI, SystemZ::LDEBR);
211       Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
215       Changed |= shortenOn001(MI, SystemZ::MDBR);
219       Changed |= shortenOn01(MI, SystemZ::LCDFR);
223       Changed |= shortenOn01(MI, SystemZ::LNDFR);
227       Changed |= shortenOn01(MI, SystemZ::LPDFR);
231       Changed |= shortenOn01(MI, SystemZ::SQDBR);
235       Changed |= shortenOn001AddCC(MI, SystemZ::SDBR);
239       Changed |= shortenOn01(MI, SystemZ::CDBR);
244       Changed |= shortenOn0(MI, SystemZ::LDE32);
248       Changed |= shortenOn0(MI, SystemZ::STE);
252       Changed |= shortenOn0(MI, SystemZ::LD);
256       Changed |= shortenOn0(MI, SystemZ::STD);
260     LiveRegs.stepBackward(MI);