/freebsd-11.0-release/contrib/llvm/lib/CodeGen/SelectionDAG/ |
H A D | TargetLowering.cpp | 2119 TargetLowering::getConstraintType(StringRef Constraint) const { 2120 unsigned S = Constraint.size(); 2123 switch (Constraint[0]) { 2151 if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { 2152 if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}" 2173 std::string &Constraint, 2177 if (Constraint.length() > 1) return; 2179 char ConstraintLetter = Constraint[0]; 2239 StringRef Constraint, 2172 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument 2238 getRegForInlineAsmConstraint(const TargetRegisterInfo *RI, StringRef Constraint, MVT VT) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Sparc/ |
H A D | SparcISelLowering.cpp | 3202 SparcTargetLowering::getConstraintType(StringRef Constraint) const { 3203 if (Constraint.size() == 1) { 3204 switch (Constraint[0]) { 3212 return TargetLowering::getConstraintType(Constraint); 3244 std::string &Constraint, 3250 if (Constraint.length() > 1) 3253 char ConstraintLetter = Constraint[0]; 3271 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3276 StringRef Constraint, 3278 if (Constraint 3243 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument 3275 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/ |
H A D | ExprEngineC.cpp | 982 DefinedOrUnknownSVal Constraint = local 985 if (!state->assume(Constraint, true)) { 988 Constraint = svalBuilder.evalEQ(state, SymVal, 992 state = state->assume(Constraint, false);
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H A D | BugReporterVisitors.cpp | 711 ID.Add(Constraint); 722 return N->getState()->isNull(Constraint).isUnderconstrained(); 723 return (bool)N->getState()->assume(Constraint, !Assumption); 758 if (Constraint.getAs<Loc>()) {
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H A D | ExprEngine.cpp | 135 Optional<DefinedOrUnknownSVal> Constraint = local 138 if (!Constraint) 141 if (ProgramStateRef newState = state->assume(*Constraint, true))
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/freebsd-11.0-release/crypto/heimdal/lib/asn1/ |
H A D | asn1parse.y | 227 %type <constraint_spec> Constraint 575 ConstrainedType : Type Constraint 577 /* if (Constraint.type == contentConstrant) { 578 assert(Constraint.u.constraint.type == octetstring|bitstring-w/o-NamedBitList); // remember to check type reference too 579 if (Constraint.u.constraint.type) { 580 assert((Constraint.u.constraint.type.length % 8) == 0); 583 if (Constraint.u.constraint.encoding) { 591 Constraint : '(' ConstraintSpec ')' label
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/Parse/ |
H A D | ParseStmtAsm.cpp | 792 ExprResult Constraint(ParseAsmStringLiteral()); 793 if (Constraint.isInvalid()) { 797 Constraints.push_back(Constraint.get());
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/freebsd-11.0-release/contrib/llvm/lib/Target/AMDGPU/ |
H A D | SIISelLowering.cpp | 2574 StringRef Constraint, 2577 if (Constraint.size() == 1) { 2578 switch (Constraint[0]) { 2614 if (Constraint.size() > 1) { 2616 if (Constraint[1] == 'v') { 2618 } else if (Constraint[1] == 's') { 2624 bool Failed = Constraint.substr(2).getAsInteger(10, Idx); 2629 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 2633 SITargetLowering::getConstraintType(StringRef Constraint) const { 2634 if (Constraint 2573 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/X86/ |
H A D | X86ISelLowering.h | 743 ConstraintType getConstraintType(StringRef Constraint) const override; 757 std::string &Constraint, 780 StringRef Constraint, MVT VT) const override;
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H A D | X86ISelLowering.cpp | [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 3225 MipsTargetLowering::getConstraintType(StringRef Constraint) const { 3237 if (Constraint.size() == 1) { 3238 switch (Constraint[0]) { 3252 if (Constraint == "ZC") 3255 return TargetLowering::getConstraintType(Constraint); 3414 StringRef Constraint, 3416 if (Constraint.size() == 1) { 3417 switch (Constraint[0]) { 3466 R = parseRegForInlineAsmConstraint(Constraint, VT); 3471 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, V 3413 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument 3476 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue>&Ops, SelectionDAG &DAG) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/SystemZ/ |
H A D | SystemZISelLowering.cpp | 548 SystemZTargetLowering::getConstraintType(StringRef Constraint) const { 549 if (Constraint.size() == 1) { 550 switch (Constraint[0]) { 576 return TargetLowering::getConstraintType(Constraint); 645 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC, argument 647 assert(*(Constraint.end()-1) == '}' && "Missing '}'"); 648 if (isdigit(Constraint[2])) { 651 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index); 660 const TargetRegisterInfo *TRI, StringRef Constraint, MV 659 getRegForInlineAsmConstraint( const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument 721 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/utils/TableGen/ |
H A D | AsmMatcherEmitter.cpp | 492 void formTwoOperandAlias(StringRef Constraint); 760 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) { argument 763 parseTwoOperandConstraint(Constraint, TheDef->getLoc()); 1507 std::string Constraint = local 1509 if (Constraint != "") { 1514 AliasII->formTwoOperandAlias(Constraint);
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H A D | X86RecognizableInstr.cpp | 529 const CGIOperandList::ConstraintInfo &Constraint = 531 if (Constraint.isTied()) { 533 operandMapping[Constraint.getTiedOperand()] = operandIndex;
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H A D | CodeGenDAGPatterns.cpp | 1187 for (const SDTypeConstraint &Constraint : TypeConstraints) { 1189 if (Constraint.OperandNo >= NumResults) // FIXME: need value # 1192 switch (Constraint.ConstraintType) { 1195 return Constraint.x.SDTCisVT_Info.VT;
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/freebsd-11.0-release/contrib/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 2528 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, 2530 if (Constraint.length() > 1) 2533 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3749 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const { 3750 if (Constraint.size() == 1) { 3751 switch (Constraint[0]) { 3766 return TargetLowering::getConstraintType(Constraint); 3771 StringRef Constraint, 3773 if (Constraint.size() == 1) { 3774 switch (Constraint[ [all...] |
/freebsd-11.0-release/contrib/llvm/include/llvm/Target/ |
H A D | TargetLowering.h | 2641 C_Register, // Constraint represents specific register(s). 2642 C_RegisterClass, // Constraint represents any of register(s) in class. 2727 virtual ConstraintType getConstraintType(StringRef Constraint) const; 2740 StringRef Constraint, MVT VT) const; 2757 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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/freebsd-11.0-release/contrib/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1966 StringRef Constraint, 1968 if (Constraint.size() == 1) { 1969 switch (Constraint[0]) { 1977 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 1965 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument
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/freebsd-11.0-release/contrib/llvm/tools/clang/lib/AST/ |
H A D | Stmt.cpp | 747 [&](StringRef Constraint) { 748 return copyIntoContext(C, Constraint);
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/freebsd-11.0-release/contrib/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 10833 PPCTargetLowering::getConstraintType(StringRef Constraint) const { 10834 if (Constraint.size() == 1) { 10835 switch (Constraint[0]) { 10852 } else if (Constraint == "wc") { // individual CR bits. 10854 } else if (Constraint == "wa" || Constraint == "wd" || 10855 Constraint == "wf" || Constraint == "ws") { 10858 return TargetLowering::getConstraintType(Constraint); 10918 StringRef Constraint, 10917 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument 10990 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue>&Ops, SelectionDAG &DAG) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/tools/clang/lib/CodeGen/ |
H A D | CGObjCMac.cpp | 3739 std::string Constraint; local 3741 if (I) Constraint += ','; 3742 Constraint += "*m"; 3745 ReadHazard = llvm::InlineAsm::get(AsmFnTy, "", Constraint, true, false); 3753 std::string Constraint; local 3755 if (I) Constraint += ','; 3756 Constraint += "=*m"; 3759 WriteHazard = llvm::InlineAsm::get(AsmFnTy, "", Constraint, true, false);
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H A D | TargetInfo.cpp | 749 StringRef Constraint, 751 if ((Constraint == "y" || Constraint == "&y") && Ty->isVectorTy()) { 902 StringRef Constraint, 904 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 1872 StringRef Constraint, 1874 return X86AdjustInlineAsmType(CGF, Constraint, Ty); 748 X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, StringRef Constraint, llvm::Type* Ty) argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.cpp | 4555 AArch64TargetLowering::getConstraintType(StringRef Constraint) const { 4556 if (Constraint.size() == 1) { 4557 switch (Constraint[0]) { 4571 return TargetLowering::getConstraintType(Constraint); 4606 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { 4607 if (Constraint.size() == 1) { 4608 switch (Constraint[0]) { 4629 if (StringRef("{cc}").equals_lower(Constraint)) 4635 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 4639 unsigned Size = Constraint 4605 getRegForInlineAsmConstraint( const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument 4659 LowerAsmOperandForConstraint( SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument [all...] |
/freebsd-11.0-release/contrib/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 2646 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { 2649 if (Constraint.size() == 1) { 2650 switch (Constraint[0]) { 2705 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT); 2645 getRegForInlineAsmConstraint( const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument
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/freebsd-11.0-release/contrib/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 11328 ARMTargetLowering::getConstraintType(StringRef Constraint) const { 11329 if (Constraint.size() == 1) { 11330 switch (Constraint[0]) { 11342 } else if (Constraint.size() == 2) { 11343 switch (Constraint[0]) { 11349 return TargetLowering::getConstraintType(Constraint); 11388 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const { 11389 if (Constraint.size() == 1) { 11390 // GCC ARM Constraint Letters 11391 switch (Constraint[ 11387 getRegForInlineAsmConstraint( const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const argument 11438 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector<SDValue>&Ops, SelectionDAG &DAG) const argument [all...] |