1193323Sed//===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file defines the interfaces that X86 uses to lower LLVM code into a 11193323Sed// selection DAG. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15280031Sdim#ifndef LLVM_LIB_TARGET_X86_X86ISELLOWERING_H 16280031Sdim#define LLVM_LIB_TARGET_X86_X86ISELLOWERING_H 17193323Sed 18249423Sdim#include "llvm/CodeGen/CallingConvLower.h" 19249423Sdim#include "llvm/CodeGen/SelectionDAG.h" 20193323Sed#include "llvm/Target/TargetLowering.h" 21203954Srdivacky#include "llvm/Target/TargetOptions.h" 22193323Sed 23193323Sednamespace llvm { 24276479Sdim class X86Subtarget; 25276479Sdim class X86TargetMachine; 26276479Sdim 27193323Sed namespace X86ISD { 28193323Sed // X86 Specific DAG Nodes 29288943Sdim enum NodeType : unsigned { 30193323Sed // Start the numbering where the builtin ops leave off. 31193323Sed FIRST_NUMBER = ISD::BUILTIN_OP_END, 32193323Sed 33288943Sdim /// Bit scan forward. 34193323Sed BSF, 35288943Sdim /// Bit scan reverse. 36193323Sed BSR, 37193323Sed 38288943Sdim /// Double shift instructions. These correspond to 39193323Sed /// X86::SHLDxx and X86::SHRDxx instructions. 40193323Sed SHLD, 41193323Sed SHRD, 42193323Sed 43288943Sdim /// Bitwise logical AND of floating point values. This corresponds 44193323Sed /// to X86::ANDPS or X86::ANDPD. 45193323Sed FAND, 46193323Sed 47288943Sdim /// Bitwise logical OR of floating point values. This corresponds 48193323Sed /// to X86::ORPS or X86::ORPD. 49193323Sed FOR, 50193323Sed 51288943Sdim /// Bitwise logical XOR of floating point values. This corresponds 52193323Sed /// to X86::XORPS or X86::XORPD. 53193323Sed FXOR, 54193323Sed 55288943Sdim /// Bitwise logical ANDNOT of floating point values. This 56261991Sdim /// corresponds to X86::ANDNPS or X86::ANDNPD. 57261991Sdim FANDN, 58261991Sdim 59288943Sdim /// These operations represent an abstract X86 call 60193323Sed /// instruction, which includes a bunch of information. In particular the 61193323Sed /// operands of these node are: 62193323Sed /// 63193323Sed /// #0 - The incoming token chain 64193323Sed /// #1 - The callee 65193323Sed /// #2 - The number of arg bytes the caller pushes on the stack. 66193323Sed /// #3 - The number of arg bytes the callee pops off the stack. 67193323Sed /// #4 - The value to pass in AL/AX/EAX (optional) 68193323Sed /// #5 - The value to pass in DL/DX/EDX (optional) 69193323Sed /// 70193323Sed /// The result values of these nodes are: 71193323Sed /// 72193323Sed /// #0 - The outgoing token chain 73193323Sed /// #1 - The first register result value (optional) 74193323Sed /// #2 - The second register result value (optional) 75193323Sed /// 76193323Sed CALL, 77198090Srdivacky 78288943Sdim /// This operation implements the lowering for readcyclecounter 79193323Sed RDTSC_DAG, 80193323Sed 81276479Sdim /// X86 Read Time-Stamp Counter and Processor ID. 82276479Sdim RDTSCP_DAG, 83276479Sdim 84276479Sdim /// X86 Read Performance Monitoring Counters. 85276479Sdim RDPMC_DAG, 86276479Sdim 87193323Sed /// X86 compare and logical compare instructions. 88193323Sed CMP, COMI, UCOMI, 89193323Sed 90193323Sed /// X86 bit-test instructions. 91193323Sed BT, 92193323Sed 93218893Sdim /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS 94218893Sdim /// operand, usually produced by a CMP instruction. 95193323Sed SETCC, 96193323Sed 97276479Sdim /// X86 Select 98276479Sdim SELECT, 99276479Sdim 100200581Srdivacky // Same as SETCC except it's materialized with a sbb and the value is all 101200581Srdivacky // one's or all zero's. 102218893Sdim SETCC_CARRY, // R = carry_bit ? ~0 : 0 103200581Srdivacky 104223017Sdim /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. 105223017Sdim /// Operands are two FP values to compare; result is a mask of 106223017Sdim /// 0s or 1s. Generally DTRT for C/C++ with NaNs. 107276479Sdim FSETCC, 108223017Sdim 109223017Sdim /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, 110223017Sdim /// result in an integer GPR. Needs masking for scalar result. 111223017Sdim FGETSIGNx86, 112223017Sdim 113193323Sed /// X86 conditional moves. Operand 0 and operand 1 are the two values 114193323Sed /// to select from. Operand 2 is the condition code, and operand 3 is the 115193323Sed /// flag operand produced by a CMP or TEST instruction. It also writes a 116193323Sed /// flag result. 117193323Sed CMOV, 118193323Sed 119193323Sed /// X86 conditional branches. Operand 0 is the chain operand, operand 1 120193323Sed /// is the block to branch if condition is true, operand 2 is the 121193323Sed /// condition code, and operand 3 is the flag operand produced by a CMP 122193323Sed /// or TEST instruction. 123193323Sed BRCOND, 124193323Sed 125193323Sed /// Return with a flag operand. Operand 0 is the chain operand, operand 126193323Sed /// 1 is the number of bytes of stack to pop. 127193323Sed RET_FLAG, 128193323Sed 129296417Sdim /// Return from interrupt. Operand 0 is the number of bytes to pop. 130296417Sdim IRET, 131296417Sdim 132288943Sdim /// Repeat fill, corresponds to X86::REP_STOSx. 133193323Sed REP_STOS, 134193323Sed 135288943Sdim /// Repeat move, corresponds to X86::REP_MOVSx. 136193323Sed REP_MOVS, 137193323Sed 138288943Sdim /// On Darwin, this node represents the result of the popl 139193323Sed /// at function entry, used for PIC code. 140193323Sed GlobalBaseReg, 141193323Sed 142288943Sdim /// A wrapper node for TargetConstantPool, 143193323Sed /// TargetExternalSymbol, and TargetGlobalAddress. 144193323Sed Wrapper, 145193323Sed 146288943Sdim /// Special wrapper used under X86-64 PIC mode for RIP 147193323Sed /// relative displacements. 148193323Sed WrapperRIP, 149193323Sed 150288943Sdim /// Copies a 64-bit value from the low word of an XMM vector 151218893Sdim /// to an MMX vector. If you think this is too close to the previous 152218893Sdim /// mnemonic, so do I; blame Intel. 153218893Sdim MOVDQ2Q, 154218893Sdim 155288943Sdim /// Copies a 32-bit value from the low word of a MMX 156243830Sdim /// vector to a GPR. 157243830Sdim MMX_MOVD2W, 158243830Sdim 159288943Sdim /// Copies a GPR into the low 32-bit word of a MMX vector 160288943Sdim /// and zero out the high word. 161288943Sdim MMX_MOVW2D, 162288943Sdim 163288943Sdim /// Extract an 8-bit value from a vector and zero extend it to 164193323Sed /// i32, corresponds to X86::PEXTRB. 165193323Sed PEXTRB, 166193323Sed 167288943Sdim /// Extract a 16-bit value from a vector and zero extend it to 168193323Sed /// i32, corresponds to X86::PEXTRW. 169193323Sed PEXTRW, 170193323Sed 171288943Sdim /// Insert any element of a 4 x float vector into any element 172193323Sed /// of a destination 4 x floatvector. 173193323Sed INSERTPS, 174193323Sed 175288943Sdim /// Insert the lower 8-bits of a 32-bit value to a vector, 176193323Sed /// corresponds to X86::PINSRB. 177193323Sed PINSRB, 178193323Sed 179288943Sdim /// Insert the lower 16-bits of a 32-bit value to a vector, 180193323Sed /// corresponds to X86::PINSRW. 181204642Srdivacky PINSRW, MMX_PINSRW, 182193323Sed 183288943Sdim /// Shuffle 16 8-bit values within a vector. 184193323Sed PSHUFB, 185219077Sdim 186288943Sdim /// Compute Sum of Absolute Differences. 187288943Sdim PSADBW, 188296417Sdim /// Compute Double Block Packed Sum-Absolute-Differences 189296417Sdim DBPSADBW, 190288943Sdim 191288943Sdim /// Bitwise Logical AND NOT of Packed FP values. 192224145Sdim ANDNP, 193219077Sdim 194288943Sdim /// Copy integer sign. 195234353Sdim PSIGN, 196219077Sdim 197288943Sdim /// Blend where the selector is an immediate. 198249423Sdim BLENDI, 199234353Sdim 200288943Sdim /// Blend where the condition has been shrunk. 201280031Sdim /// This is used to emphasize that the condition mask is 202280031Sdim /// no more valid for generic VSELECT optimizations. 203280031Sdim SHRUNKBLEND, 204280031Sdim 205288943Sdim /// Combined add and sub on an FP vector. 206280031Sdim ADDSUB, 207280031Sdim 208288943Sdim // FP vector ops with rounding mode. 209288943Sdim FADD_RND, 210288943Sdim FSUB_RND, 211288943Sdim FMUL_RND, 212288943Sdim FDIV_RND, 213288943Sdim FMAX_RND, 214288943Sdim FMIN_RND, 215288943Sdim FSQRT_RND, 216288943Sdim 217288943Sdim // FP vector get exponent 218288943Sdim FGETEXP_RND, 219296417Sdim // Extract Normalized Mantissas 220296417Sdim VGETMANT, 221288943Sdim // FP Scale 222288943Sdim SCALEF, 223288943Sdim // Integer add/sub with unsigned saturation. 224288943Sdim ADDUS, 225249423Sdim SUBUS, 226288943Sdim // Integer add/sub with signed saturation. 227288943Sdim ADDS, 228288943Sdim SUBS, 229288943Sdim // Unsigned Integer average 230288943Sdim AVG, 231288943Sdim /// Integer horizontal add. 232234353Sdim HADD, 233234353Sdim 234288943Sdim /// Integer horizontal sub. 235234353Sdim HSUB, 236234353Sdim 237288943Sdim /// Floating point horizontal add. 238226633Sdim FHADD, 239226633Sdim 240288943Sdim /// Floating point horizontal sub. 241226633Sdim FHSUB, 242226633Sdim 243288943Sdim // Integer absolute value 244288943Sdim ABS, 245249423Sdim 246296417Sdim // Detect Conflicts Within a Vector 247296417Sdim CONFLICT, 248296417Sdim 249288943Sdim /// Floating point max and min. 250193323Sed FMAX, FMIN, 251193323Sed 252288943Sdim /// Commutative FMIN and FMAX. 253243830Sdim FMAXC, FMINC, 254243830Sdim 255288943Sdim /// Floating point reciprocal-sqrt and reciprocal approximation. 256288943Sdim /// Note that these typically require refinement 257193323Sed /// in order to obtain suitable precision. 258193323Sed FRSQRT, FRCP, 259193323Sed 260288943Sdim // Thread Local Storage. 261193323Sed TLSADDR, 262218893Sdim 263288943Sdim // Thread Local Storage. A call to get the start address 264239462Sdim // of the TLS block for the current module. 265239462Sdim TLSBASEADDR, 266239462Sdim 267288943Sdim // Thread Local Storage. When calling to an OS provided 268210299Sed // thunk at the address from an earlier relocation. 269210299Sed TLSCALL, 270193323Sed 271288943Sdim // Exception Handling helpers. 272193323Sed EH_RETURN, 273218893Sdim 274288943Sdim // SjLj exception handling setjmp. 275243830Sdim EH_SJLJ_SETJMP, 276243830Sdim 277288943Sdim // SjLj exception handling longjmp. 278243830Sdim EH_SJLJ_LONGJMP, 279243830Sdim 280288943Sdim /// Tail call return. See X86TargetLowering::LowerCall for 281249423Sdim /// the list of operands. 282193323Sed TC_RETURN, 283193323Sed 284288943Sdim // Vector move to low scalar and zero higher vector elements. 285193323Sed VZEXT_MOVL, 286193323Sed 287288943Sdim // Vector integer zero-extend. 288243830Sdim VZEXT, 289243830Sdim 290288943Sdim // Vector integer signed-extend. 291243830Sdim VSEXT, 292243830Sdim 293288943Sdim // Vector integer truncate. 294261991Sdim VTRUNC, 295296417Sdim // Vector integer truncate with unsigned/signed saturation. 296296417Sdim VTRUNCUS, VTRUNCS, 297261991Sdim 298288943Sdim // Vector FP extend. 299239462Sdim VFPEXT, 300239462Sdim 301288943Sdim // Vector FP round. 302243830Sdim VFPROUND, 303243830Sdim 304288943Sdim // Vector signed/unsigned integer to double. 305288943Sdim CVTDQ2PD, CVTUDQ2PD, 306288943Sdim 307296417Sdim // Convert a vector to mask, set bits base on MSB. 308296417Sdim CVT2MASK, 309296417Sdim 310288943Sdim // 128-bit vector logical left / right shift 311234353Sdim VSHLDQ, VSRLDQ, 312218893Sdim 313288943Sdim // Vector shift elements 314234353Sdim VSHL, VSRL, VSRA, 315234353Sdim 316288943Sdim // Vector shift elements by immediate 317234353Sdim VSHLI, VSRLI, VSRAI, 318234353Sdim 319296417Sdim // Bit rotate by immediate 320296417Sdim VROTLI, VROTRI, 321296417Sdim 322288943Sdim // Vector packed double/float comparison. 323234353Sdim CMPP, 324234353Sdim 325288943Sdim // Vector integer comparisons. 326234353Sdim PCMPEQ, PCMPGT, 327288943Sdim // Vector integer comparisons, the result is in a mask vector. 328261991Sdim PCMPEQM, PCMPGTM, 329193323Sed 330288943Sdim /// Vector comparison generating mask bits for fp and 331261991Sdim /// integer signed and unsigned data types. 332261991Sdim CMPM, 333261991Sdim CMPMU, 334288943Sdim // Vector comparison with rounding mode for FP values 335288943Sdim CMPM_RND, 336261991Sdim 337288943Sdim // Arithmetic operations with FLAGS results. 338218893Sdim ADD, SUB, ADC, SBB, SMUL, 339198090Srdivacky INC, DEC, OR, XOR, AND, 340219077Sdim 341288943Sdim BEXTR, // Bit field extract 342234353Sdim 343218893Sdim UMUL, // LOW, HI, FLAGS = umul LHS, RHS 344193323Sed 345280031Sdim // 8-bit SMUL/UMUL - AX, FLAGS = smul8/umul8 AL, RHS 346280031Sdim SMUL8, UMUL8, 347280031Sdim 348280031Sdim // 8-bit divrem that zero-extend the high result (AH). 349280031Sdim UDIVREM8_ZEXT_HREG, 350280031Sdim SDIVREM8_SEXT_HREG, 351280031Sdim 352288943Sdim // X86-specific multiply by immediate. 353198090Srdivacky MUL_IMM, 354218893Sdim 355288943Sdim // Vector bitwise comparisons. 356198090Srdivacky PTEST, 357198090Srdivacky 358288943Sdim // Vector packed fp sign bitwise comparisons. 359212904Sdim TESTP, 360212904Sdim 361288943Sdim // Vector "test" in AVX-512, the result is in a mask vector. 362261991Sdim TESTM, 363276479Sdim TESTNM, 364261991Sdim 365261991Sdim // OR/AND test for masks 366261991Sdim KORTEST, 367296417Sdim KTEST, 368261991Sdim 369212904Sdim // Several flavors of instructions with vector shuffle behaviors. 370276479Sdim PACKSS, 371276479Sdim PACKUS, 372280031Sdim // Intra-lane alignr 373249423Sdim PALIGNR, 374280031Sdim // AVX512 inter-lane alignr 375280031Sdim VALIGN, 376212904Sdim PSHUFD, 377212904Sdim PSHUFHW, 378212904Sdim PSHUFLW, 379234353Sdim SHUFP, 380288943Sdim //Shuffle Packed Values at 128-bit granularity 381288943Sdim SHUF128, 382212904Sdim MOVDDUP, 383212904Sdim MOVSHDUP, 384212904Sdim MOVSLDUP, 385212904Sdim MOVLHPS, 386212904Sdim MOVLHPD, 387212904Sdim MOVHLPS, 388212904Sdim MOVLPS, 389212904Sdim MOVLPD, 390212904Sdim MOVSD, 391212904Sdim MOVSS, 392234353Sdim UNPCKL, 393234353Sdim UNPCKH, 394280031Sdim VPERMILPV, 395280031Sdim VPERMILPI, 396234982Sdim VPERMV, 397261991Sdim VPERMV3, 398276479Sdim VPERMIV3, 399234982Sdim VPERMI, 400234353Sdim VPERM2X128, 401296417Sdim // Bitwise ternary logic 402296417Sdim VPTERNLOG, 403296417Sdim // Fix Up Special Packed Float32/64 values 404288943Sdim VFIXUPIMM, 405296417Sdim // Range Restriction Calculation For Packed Pairs of Float32/64 values 406288943Sdim VRANGE, 407296417Sdim // Reduce - Perform Reduction Transformation on scalar\packed FP 408296417Sdim VREDUCE, 409296417Sdim // RndScale - Round FP Values To Include A Given Number Of Fraction Bits 410296417Sdim VRNDSCALE, 411296417Sdim // VFPCLASS - Tests Types Of a FP Values for packed types. 412296417Sdim VFPCLASS, 413296417Sdim // VFPCLASSS - Tests Types Of a FP Values for scalar types. 414296417Sdim VFPCLASSS, 415288943Sdim // Broadcast scalar to vector 416226633Sdim VBROADCAST, 417296417Sdim // Broadcast mask to vector 418296417Sdim VBROADCASTM, 419288943Sdim // Broadcast subvector to vector 420288943Sdim SUBV_BROADCAST, 421276479Sdim // Insert/Extract vector element 422261991Sdim VINSERT, 423276479Sdim VEXTRACT, 424212904Sdim 425288943Sdim /// SSE4A Extraction and Insertion. 426288943Sdim EXTRQI, INSERTQI, 427288943Sdim 428296417Sdim // XOP variable/immediate rotations 429296417Sdim VPROT, VPROTI, 430296417Sdim // XOP arithmetic/logical shifts 431296417Sdim VPSHA, VPSHL, 432296417Sdim // XOP signed/unsigned integer comparisons 433296417Sdim VPCOM, VPCOMU, 434296417Sdim 435280031Sdim // Vector multiply packed unsigned doubleword integers 436234353Sdim PMULUDQ, 437280031Sdim // Vector multiply packed signed doubleword integers 438276479Sdim PMULDQ, 439288943Sdim // Vector Multiply Packed UnsignedIntegers with Round and Scale 440288943Sdim MULHRS, 441296417Sdim // Multiply and Add Packed Integers 442296417Sdim VPMADDUBSW, VPMADDWD, 443239462Sdim // FMA nodes 444239462Sdim FMADD, 445239462Sdim FNMADD, 446239462Sdim FMSUB, 447239462Sdim FNMSUB, 448239462Sdim FMADDSUB, 449239462Sdim FMSUBADD, 450288943Sdim // FMA with rounding mode 451288943Sdim FMADD_RND, 452288943Sdim FNMADD_RND, 453288943Sdim FMSUB_RND, 454288943Sdim FNMSUB_RND, 455288943Sdim FMADDSUB_RND, 456288943Sdim FMSUBADD_RND, 457239462Sdim 458280031Sdim // Compress and expand 459280031Sdim COMPRESS, 460280031Sdim EXPAND, 461280031Sdim 462288943Sdim //Convert Unsigned/Integer to Scalar Floating-Point Value 463288943Sdim //with rounding mode 464288943Sdim SINT_TO_FP_RND, 465288943Sdim UINT_TO_FP_RND, 466288943Sdim 467288943Sdim // Vector float/double to signed/unsigned integer. 468288943Sdim FP_TO_SINT_RND, FP_TO_UINT_RND, 469280031Sdim // Save xmm argument registers to the stack, according to %al. An operator 470280031Sdim // is needed so that this can be expanded with control flow. 471198090Srdivacky VASTART_SAVE_XMM_REGS, 472198090Srdivacky 473280031Sdim // Windows's _chkstk call to do stack probing. 474218893Sdim WIN_ALLOCA, 475204961Srdivacky 476280031Sdim // For allocating variable amounts of stack space when using 477226633Sdim // segmented stacks. Check if the current stacklet has enough space, and 478226633Sdim // falls back to heap allocation if not. 479226633Sdim SEG_ALLOCA, 480226633Sdim 481218893Sdim // Memory barrier 482218893Sdim MEMBARRIER, 483218893Sdim MFENCE, 484218893Sdim SFENCE, 485218893Sdim LFENCE, 486218893Sdim 487280031Sdim // Store FP status word into i16 register. 488239462Sdim FNSTSW16r, 489239462Sdim 490280031Sdim // Store contents of %ah into %eflags. 491239462Sdim SAHF, 492239462Sdim 493280031Sdim // Get a random integer and indicate whether it is valid in CF. 494239462Sdim RDRAND, 495239462Sdim 496280031Sdim // Get a NIST SP800-90B & C compliant random integer and 497249423Sdim // indicate whether it is valid in CF. 498249423Sdim RDSEED, 499249423Sdim 500239462Sdim PCMPISTRI, 501239462Sdim PCMPESTRI, 502239462Sdim 503280031Sdim // Test if in transactional execution. 504249423Sdim XTEST, 505249423Sdim 506280031Sdim // ERI instructions 507280031Sdim RSQRT28, RCP28, EXP2, 508280031Sdim 509280031Sdim // Compare and swap. 510276479Sdim LCMPXCHG_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, 511218893Sdim LCMPXCHG8_DAG, 512226633Sdim LCMPXCHG16_DAG, 513218893Sdim 514280031Sdim // Load, scalar_to_vector, and zero extend. 515218893Sdim VZEXT_LOAD, 516218893Sdim 517280031Sdim // Store FP control world into i16 memory. 518218893Sdim FNSTCW16m, 519218893Sdim 520280031Sdim /// This instruction implements FP_TO_SINT with the 521218893Sdim /// integer destination in memory and a FP reg source. This corresponds 522218893Sdim /// to the X86::FIST*m instructions and the rounding mode change stuff. It 523218893Sdim /// has two inputs (token chain and address) and two outputs (int value 524218893Sdim /// and token chain). 525218893Sdim FP_TO_INT16_IN_MEM, 526218893Sdim FP_TO_INT32_IN_MEM, 527218893Sdim FP_TO_INT64_IN_MEM, 528218893Sdim 529280031Sdim /// This instruction implements SINT_TO_FP with the 530218893Sdim /// integer source in memory and FP reg result. This corresponds to the 531218893Sdim /// X86::FILD*m instructions. It has three inputs (token chain, address, 532218893Sdim /// and source type) and two outputs (FP value and token chain). FILD_FLAG 533218893Sdim /// also produces a flag). 534218893Sdim FILD, 535218893Sdim FILD_FLAG, 536218893Sdim 537280031Sdim /// This instruction implements an extending load to FP stack slots. 538218893Sdim /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain 539218893Sdim /// operand, ptr to load from, and a ValueType node indicating the type 540218893Sdim /// to load to. 541218893Sdim FLD, 542218893Sdim 543280031Sdim /// This instruction implements a truncating store to FP stack 544218893Sdim /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a 545218893Sdim /// chain operand, value to store, address, and a ValueType to store it 546218893Sdim /// as. 547218893Sdim FST, 548218893Sdim 549280031Sdim /// This instruction grabs the address of the next argument 550218893Sdim /// from a va_list. (reads and modifies the va_list in memory) 551218893Sdim VAARG_64 552218893Sdim 553204961Srdivacky // WARNING: Do not add anything in the end unless you want the node to 554204961Srdivacky // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be 555204961Srdivacky // thought as target memory ops! 556193323Sed }; 557193323Sed } 558193323Sed 559193323Sed /// Define some predicates that are used for node matching. 560193323Sed namespace X86 { 561280031Sdim /// Return true if the specified 562218893Sdim /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 563261991Sdim /// suitable for input to VEXTRACTF128, VEXTRACTI128 instructions. 564261991Sdim bool isVEXTRACT128Index(SDNode *N); 565218893Sdim 566280031Sdim /// Return true if the specified 567218893Sdim /// INSERT_SUBVECTOR operand specifies a subvector insert that is 568261991Sdim /// suitable for input to VINSERTF128, VINSERTI128 instructions. 569261991Sdim bool isVINSERT128Index(SDNode *N); 570218893Sdim 571280031Sdim /// Return true if the specified 572261991Sdim /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 573261991Sdim /// suitable for input to VEXTRACTF64X4, VEXTRACTI64X4 instructions. 574261991Sdim bool isVEXTRACT256Index(SDNode *N); 575261991Sdim 576280031Sdim /// Return true if the specified 577261991Sdim /// INSERT_SUBVECTOR operand specifies a subvector insert that is 578261991Sdim /// suitable for input to VINSERTF64X4, VINSERTI64X4 instructions. 579261991Sdim bool isVINSERT256Index(SDNode *N); 580261991Sdim 581280031Sdim /// Return the appropriate 582218893Sdim /// immediate to extract the specified EXTRACT_SUBVECTOR index 583261991Sdim /// with VEXTRACTF128, VEXTRACTI128 instructions. 584261991Sdim unsigned getExtractVEXTRACT128Immediate(SDNode *N); 585218893Sdim 586280031Sdim /// Return the appropriate 587218893Sdim /// immediate to insert at the specified INSERT_SUBVECTOR index 588261991Sdim /// with VINSERTF128, VINSERT128 instructions. 589261991Sdim unsigned getInsertVINSERT128Immediate(SDNode *N); 590218893Sdim 591280031Sdim /// Return the appropriate 592261991Sdim /// immediate to extract the specified EXTRACT_SUBVECTOR index 593261991Sdim /// with VEXTRACTF64X4, VEXTRACTI64x4 instructions. 594261991Sdim unsigned getExtractVEXTRACT256Immediate(SDNode *N); 595261991Sdim 596280031Sdim /// Return the appropriate 597261991Sdim /// immediate to insert at the specified INSERT_SUBVECTOR index 598261991Sdim /// with VINSERTF64x4, VINSERTI64x4 instructions. 599261991Sdim unsigned getInsertVINSERT256Immediate(SDNode *N); 600261991Sdim 601280031Sdim /// Returns true if Elt is a constant zero or floating point constant +0.0. 602198090Srdivacky bool isZeroNode(SDValue Elt); 603198090Srdivacky 604280031Sdim /// Returns true of the given offset can be 605198090Srdivacky /// fit into displacement field of the instruction. 606198090Srdivacky bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 607198090Srdivacky bool hasSymbolicDisplacement = true); 608224145Sdim 609224145Sdim 610280031Sdim /// Determines whether the callee is required to pop its 611224145Sdim /// own arguments. Callee pop is necessary to support tail calls. 612224145Sdim bool isCalleePop(CallingConv::ID CallingConv, 613224145Sdim bool is64Bit, bool IsVarArg, bool TailCallOpt); 614280031Sdim 615193323Sed } 616193323Sed 617193323Sed //===--------------------------------------------------------------------===// 618280031Sdim // X86 Implementation of the TargetLowering interface 619276479Sdim class X86TargetLowering final : public TargetLowering { 620193323Sed public: 621288943Sdim explicit X86TargetLowering(const X86TargetMachine &TM, 622288943Sdim const X86Subtarget &STI); 623193323Sed 624276479Sdim unsigned getJumpTableEncoding() const override; 625288943Sdim bool useSoftFloat() const override; 626203954Srdivacky 627288943Sdim MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override { 628288943Sdim return MVT::i8; 629288943Sdim } 630219077Sdim 631276479Sdim const MCExpr * 632203954Srdivacky LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 633203954Srdivacky const MachineBasicBlock *MBB, unsigned uid, 634276479Sdim MCContext &Ctx) const override; 635218893Sdim 636280031Sdim /// Returns relocation base for the given PIC jumptable. 637276479Sdim SDValue getPICJumpTableRelocBase(SDValue Table, 638276479Sdim SelectionDAG &DAG) const override; 639276479Sdim const MCExpr * 640203954Srdivacky getPICJumpTableRelocBaseExpr(const MachineFunction *MF, 641276479Sdim unsigned JTI, MCContext &Ctx) const override; 642218893Sdim 643280031Sdim /// Return the desired alignment for ByVal aggregate 644193323Sed /// function arguments in the caller parameter area. For X86, aggregates 645193323Sed /// that contains are placed at 16-byte boundaries while the rest are at 646193323Sed /// 4-byte boundaries. 647288943Sdim unsigned getByValTypeAlignment(Type *Ty, 648288943Sdim const DataLayout &DL) const override; 649193323Sed 650280031Sdim /// Returns the target specific optimal type for load 651206124Srdivacky /// and store operations as a result of memset, memcpy, and memmove 652206124Srdivacky /// lowering. If DstAlign is zero that means it's safe to destination 653206124Srdivacky /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 654206124Srdivacky /// means there isn't a need to check it against alignment requirement, 655249423Sdim /// probably because the source does not need to be loaded. If 'IsMemset' is 656249423Sdim /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that 657249423Sdim /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy 658249423Sdim /// source is constant so it does not need to be loaded. 659207618Srdivacky /// It returns EVT::Other if the type should be determined using generic 660207618Srdivacky /// target-independent logic. 661276479Sdim EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign, 662276479Sdim bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc, 663276479Sdim MachineFunction &MF) const override; 664195340Sed 665280031Sdim /// Returns true if it's safe to use load / store of the 666249423Sdim /// specified type to expand memcpy / memset inline. This is mostly true 667249423Sdim /// for all types except for some special cases. For example, on X86 668249423Sdim /// targets without SSE2 f64 load / store are done with fldl / fstpl which 669249423Sdim /// also does type conversion. Note the specified type doesn't have to be 670249423Sdim /// legal as the hook is used before type legalization. 671276479Sdim bool isSafeMemOpType(MVT VT) const override; 672249423Sdim 673288943Sdim /// Returns true if the target allows unaligned memory accesses of the 674288943Sdim /// specified type. Returns whether it is "fast" in the last argument. 675280031Sdim bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS, unsigned Align, 676276479Sdim bool *Fast) const override; 677198090Srdivacky 678280031Sdim /// Provide custom lowering hooks for some operations. 679193323Sed /// 680276479Sdim SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 681193323Sed 682280031Sdim /// Replace the results of node with an illegal result 683193323Sed /// type with new values built out of custom code. 684193323Sed /// 685276479Sdim void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 686276479Sdim SelectionDAG &DAG) const override; 687193323Sed 688218893Sdim 689276479Sdim SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 690193323Sed 691280031Sdim /// Return true if the target has native support for 692207618Srdivacky /// the specified value type and it is 'desirable' to use the type for the 693207618Srdivacky /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 694207618Srdivacky /// instruction encodings are longer and some i16 instructions are slow. 695276479Sdim bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override; 696193323Sed 697280031Sdim /// Return true if the target has native support for the 698207618Srdivacky /// specified value type and it is 'desirable' to use the type. e.g. On x86 699207618Srdivacky /// i16 is legal, but undesirable since i16 instruction encodings are longer 700207618Srdivacky /// and some i16 instructions are slow. 701276479Sdim bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override; 702207618Srdivacky 703296417Sdim /// Return true if the MachineFunction contains a COPY which would imply 704296417Sdim /// HasOpaqueSPAdjustment. 705296417Sdim bool hasCopyImplyingStackAdjustment(MachineFunction *MF) const override; 706296417Sdim 707276479Sdim MachineBasicBlock * 708207618Srdivacky EmitInstrWithCustomInserter(MachineInstr *MI, 709276479Sdim MachineBasicBlock *MBB) const override; 710207618Srdivacky 711218893Sdim 712280031Sdim /// This method returns the name of a target specific DAG node. 713276479Sdim const char *getTargetNodeName(unsigned Opcode) const override; 714193323Sed 715280031Sdim bool isCheapToSpeculateCttz() const override; 716280031Sdim 717280031Sdim bool isCheapToSpeculateCtlz() const override; 718280031Sdim 719280031Sdim /// Return the value type to use for ISD::SETCC. 720288943Sdim EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, 721288943Sdim EVT VT) const override; 722193323Sed 723280031Sdim /// Determine which of the bits specified in Mask are known to be either 724280031Sdim /// zero or one and return them in the KnownZero/KnownOne bitsets. 725276479Sdim void computeKnownBitsForTargetNode(const SDValue Op, 726276479Sdim APInt &KnownZero, 727276479Sdim APInt &KnownOne, 728276479Sdim const SelectionDAG &DAG, 729276479Sdim unsigned Depth = 0) const override; 730193323Sed 731280031Sdim /// Determine the number of bits in the operation that are sign bits. 732276479Sdim unsigned ComputeNumSignBitsForTargetNode(SDValue Op, 733276479Sdim const SelectionDAG &DAG, 734276479Sdim unsigned Depth) const override; 735218893Sdim 736276479Sdim bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA, 737276479Sdim int64_t &Offset) const override; 738218893Sdim 739207618Srdivacky SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; 740193323Sed 741276479Sdim bool ExpandInlineAsm(CallInst *CI) const override; 742218893Sdim 743288943Sdim ConstraintType getConstraintType(StringRef Constraint) const override; 744218893Sdim 745218893Sdim /// Examine constraint string and operand type and determine a weight value. 746218893Sdim /// The operand object must already have been set up with the operand type. 747276479Sdim ConstraintWeight 748276479Sdim getSingleConstraintMatchWeight(AsmOperandInfo &info, 749276479Sdim const char *constraint) const override; 750218893Sdim 751276479Sdim const char *LowerXConstraint(EVT ConstraintVT) const override; 752193323Sed 753280031Sdim /// Lower the specified operand into the Ops vector. If it is invalid, don't 754280031Sdim /// add anything to Ops. If hasMemory is true it means one of the asm 755280031Sdim /// constraint of the inline asm instruction being processed is 'm'. 756276479Sdim void LowerAsmOperandForConstraint(SDValue Op, 757276479Sdim std::string &Constraint, 758276479Sdim std::vector<SDValue> &Ops, 759276479Sdim SelectionDAG &DAG) const override; 760218893Sdim 761288943Sdim unsigned 762288943Sdim getInlineAsmMemConstraint(StringRef ConstraintCode) const override { 763288943Sdim if (ConstraintCode == "i") 764288943Sdim return InlineAsm::Constraint_i; 765288943Sdim else if (ConstraintCode == "o") 766288943Sdim return InlineAsm::Constraint_o; 767288943Sdim else if (ConstraintCode == "v") 768288943Sdim return InlineAsm::Constraint_v; 769288943Sdim else if (ConstraintCode == "X") 770288943Sdim return InlineAsm::Constraint_X; 771288943Sdim return TargetLowering::getInlineAsmMemConstraint(ConstraintCode); 772288943Sdim } 773288943Sdim 774280031Sdim /// Given a physical register constraint 775193323Sed /// (e.g. {edx}), return the register number and the register class for the 776193323Sed /// register. This should only be used for C_Register constraints. On 777193323Sed /// error, this returns a register number of 0. 778288943Sdim std::pair<unsigned, const TargetRegisterClass *> 779288943Sdim getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, 780288943Sdim StringRef Constraint, MVT VT) const override; 781218893Sdim 782280031Sdim /// Return true if the addressing mode represented 783193323Sed /// by AM is legal for this target, for a load/store of the specified type. 784288943Sdim bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, 785288943Sdim Type *Ty, unsigned AS) const override; 786193323Sed 787280031Sdim /// Return true if the specified immediate is legal 788239462Sdim /// icmp immediate, that is the target has icmp instructions which can 789239462Sdim /// compare a register against the immediate without having to materialize 790239462Sdim /// the immediate into a register. 791276479Sdim bool isLegalICmpImmediate(int64_t Imm) const override; 792239462Sdim 793280031Sdim /// Return true if the specified immediate is legal 794239462Sdim /// add immediate, that is the target has add instructions which can 795239462Sdim /// add a register and the immediate without having to materialize 796239462Sdim /// the immediate into a register. 797276479Sdim bool isLegalAddImmediate(int64_t Imm) const override; 798239462Sdim 799276479Sdim /// \brief Return the cost of the scaling factor used in the addressing 800276479Sdim /// mode represented by AM for this target, for a load/store 801276479Sdim /// of the specified type. 802276479Sdim /// If the AM is supported, the return value must be >= 0. 803276479Sdim /// If the AM is not supported, it returns a negative value. 804288943Sdim int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty, 805288943Sdim unsigned AS) const override; 806276479Sdim 807276479Sdim bool isVectorShiftByScalarCheap(Type *Ty) const override; 808276479Sdim 809280031Sdim /// Return true if it's free to truncate a value of 810193323Sed /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in 811193323Sed /// register EAX to i16 by referencing its sub-register AX. 812276479Sdim bool isTruncateFree(Type *Ty1, Type *Ty2) const override; 813276479Sdim bool isTruncateFree(EVT VT1, EVT VT2) const override; 814193323Sed 815276479Sdim bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 816261991Sdim 817280031Sdim /// Return true if any actual instruction that defines a 818193323Sed /// value of type Ty1 implicit zero-extends the value to Ty2 in the result 819193323Sed /// register. This does not necessarily include registers defined in 820193323Sed /// unknown ways, such as incoming arguments, or copies from unknown 821193323Sed /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this 822193323Sed /// does not necessarily apply to truncate instructions. e.g. on x86-64, 823193323Sed /// all instructions that define 32-bit values implicit zero-extend the 824193323Sed /// result out to 64 bits. 825276479Sdim bool isZExtFree(Type *Ty1, Type *Ty2) const override; 826276479Sdim bool isZExtFree(EVT VT1, EVT VT2) const override; 827276479Sdim bool isZExtFree(SDValue Val, EVT VT2) const override; 828193323Sed 829288943Sdim /// Return true if folding a vector load into ExtVal (a sign, zero, or any 830288943Sdim /// extend node) is profitable. 831288943Sdim bool isVectorLoadExtDesirable(SDValue) const override; 832288943Sdim 833280031Sdim /// Return true if an FMA operation is faster than a pair of fmul and fadd 834280031Sdim /// instructions. fmuladd intrinsics will be expanded to FMAs when this 835280031Sdim /// method returns true, otherwise fmuladd is expanded to fmul + fadd. 836276479Sdim bool isFMAFasterThanFMulAndFAdd(EVT VT) const override; 837239462Sdim 838280031Sdim /// Return true if it's profitable to narrow 839193323Sed /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow 840193323Sed /// from i32 to i8 but not from i32 to i16. 841276479Sdim bool isNarrowingProfitable(EVT VT1, EVT VT2) const override; 842193323Sed 843296417Sdim /// Given an intrinsic, checks if on the target the intrinsic will need to map 844296417Sdim /// to a MemIntrinsicNode (touches memory). If this is the case, it returns 845296417Sdim /// true and stores the intrinsic information into the IntrinsicInfo that was 846296417Sdim /// passed to the function. 847296417Sdim bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I, 848296417Sdim unsigned Intrinsic) const override; 849296417Sdim 850280031Sdim /// Returns true if the target can instruction select the 851198892Srdivacky /// specified FP immediate natively. If false, the legalizer will 852198892Srdivacky /// materialize the FP immediate as a load from a constant pool. 853276479Sdim bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 854198892Srdivacky 855280031Sdim /// Targets can use this to indicate that they only support *some* 856280031Sdim /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a 857280031Sdim /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to 858280031Sdim /// be legal. 859276479Sdim bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, 860276479Sdim EVT VT) const override; 861193323Sed 862280031Sdim /// Similar to isShuffleMaskLegal. This is used by Targets can use this to 863280031Sdim /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to 864280031Sdim /// replace a VAND with a constant pool entry. 865276479Sdim bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 866276479Sdim EVT VT) const override; 867193323Sed 868280031Sdim /// If true, then instruction selection should 869193323Sed /// seek to shrink the FP constant of the specified type to a smaller type 870193323Sed /// in order to save space and / or reduce runtime. 871276479Sdim bool ShouldShrinkFPConstant(EVT VT) const override { 872193323Sed // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more 873193323Sed // expensive than a straight movsd. On the other hand, it's important to 874193323Sed // shrink long double fp constant since fldt is very slow. 875193323Sed return !X86ScalarSSEf64 || VT == MVT::f80; 876193323Sed } 877218893Sdim 878280031Sdim /// Return true if we believe it is correct and profitable to reduce the 879280031Sdim /// load node to a smaller type. 880280031Sdim bool shouldReduceLoadWidth(SDNode *Load, ISD::LoadExtType ExtTy, 881280031Sdim EVT NewVT) const override; 882280031Sdim 883280031Sdim /// Return true if the specified scalar FP type is computed in an SSE 884280031Sdim /// register, not on the X87 floating point stack. 885198090Srdivacky bool isScalarFPTypeInSSEReg(EVT VT) const { 886193323Sed return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 887296417Sdim (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 888193323Sed } 889193323Sed 890276479Sdim /// \brief Returns true if it is beneficial to convert a load of a constant 891276479Sdim /// to just the constant itself. 892276479Sdim bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 893276479Sdim Type *Ty) const override; 894276479Sdim 895280031Sdim /// Return true if EXTRACT_SUBVECTOR is cheap for this result type 896280031Sdim /// with this index. 897280031Sdim bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const override; 898280031Sdim 899276479Sdim /// Intel processors have a unified instruction and data cache 900276479Sdim const char * getClearCacheBuiltinName() const override { 901276479Sdim return nullptr; // nothing to do, move along. 902276479Sdim } 903276479Sdim 904288943Sdim unsigned getRegisterByName(const char* RegName, EVT VT, 905288943Sdim SelectionDAG &DAG) const override; 906276479Sdim 907296417Sdim /// If a physical register, this returns the register that receives the 908296417Sdim /// exception address on entry to an EH pad. 909296417Sdim unsigned 910296417Sdim getExceptionPointerRegister(const Constant *PersonalityFn) const override; 911296417Sdim 912296417Sdim /// If a physical register, this returns the register that receives the 913296417Sdim /// exception typeid on entry to a landing pad. 914296417Sdim unsigned 915296417Sdim getExceptionSelectorRegister(const Constant *PersonalityFn) const override; 916296417Sdim 917280031Sdim /// This method returns a target specific FastISel object, 918193323Sed /// or null if the target does not support "fast" ISel. 919276479Sdim FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 920276479Sdim const TargetLibraryInfo *libInfo) const override; 921195340Sed 922280031Sdim /// Return true if the target stores stack protector cookies at a fixed 923280031Sdim /// offset in some non-standard address space, and populates the address 924280031Sdim /// space and offset as appropriate. 925276479Sdim bool getStackCookieLocation(unsigned &AddressSpace, 926276479Sdim unsigned &Offset) const override; 927210299Sed 928296417Sdim /// Return true if the target stores SafeStack pointer at a fixed offset in 929296417Sdim /// some non-standard address space, and populates the address space and 930296417Sdim /// offset as appropriate. 931296417Sdim Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const override; 932296417Sdim 933223017Sdim SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, 934223017Sdim SelectionDAG &DAG) const; 935223017Sdim 936276479Sdim bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override; 937261991Sdim 938280031Sdim bool useLoadStackGuardNode() const override; 939276479Sdim /// \brief Customize the preferred legalization strategy for certain types. 940276479Sdim LegalizeTypeAction getPreferredVectorAction(EVT VT) const override; 941276479Sdim 942296417Sdim bool isIntDivCheap(EVT VT, AttributeSet Attr) const override; 943296417Sdim 944212904Sdim protected: 945288943Sdim std::pair<const TargetRegisterClass *, uint8_t> 946288943Sdim findRepresentativeClass(const TargetRegisterInfo *TRI, 947288943Sdim MVT VT) const override; 948212904Sdim 949193323Sed private: 950280031Sdim /// Keep a pointer to the X86Subtarget around so that we can 951193323Sed /// make the right decision when generating code for different targets. 952193323Sed const X86Subtarget *Subtarget; 953193323Sed 954280031Sdim /// Select between SSE or x87 floating point ops. 955193323Sed /// When SSE is available, use it for f32 operations. 956193323Sed /// When SSE2 is available, use it for f64 operations. 957193323Sed bool X86ScalarSSEf32; 958193323Sed bool X86ScalarSSEf64; 959193323Sed 960280031Sdim /// A list of legal FP immediates. 961198892Srdivacky std::vector<APFloat> LegalFPImmediates; 962198892Srdivacky 963280031Sdim /// Indicate that this x86 target can instruction 964198892Srdivacky /// select the specified FP immediate natively. 965198892Srdivacky void addLegalFPImmediate(const APFloat& Imm) { 966198892Srdivacky LegalFPImmediates.push_back(Imm); 967198892Srdivacky } 968198892Srdivacky 969198090Srdivacky SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 970198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 971198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 972261991Sdim SDLoc dl, SelectionDAG &DAG, 973207618Srdivacky SmallVectorImpl<SDValue> &InVals) const; 974198090Srdivacky SDValue LowerMemArgument(SDValue Chain, 975198090Srdivacky CallingConv::ID CallConv, 976198090Srdivacky const SmallVectorImpl<ISD::InputArg> &ArgInfo, 977261991Sdim SDLoc dl, SelectionDAG &DAG, 978198090Srdivacky const CCValAssign &VA, MachineFrameInfo *MFI, 979207618Srdivacky unsigned i) const; 980198090Srdivacky SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 981261991Sdim SDLoc dl, SelectionDAG &DAG, 982198090Srdivacky const CCValAssign &VA, 983207618Srdivacky ISD::ArgFlagsTy Flags) const; 984193323Sed 985193323Sed // Call lowering helpers. 986203954Srdivacky 987280031Sdim /// Check whether the call is eligible for tail call optimization. Targets 988280031Sdim /// that want to do tail call optimization should implement this function. 989203954Srdivacky bool IsEligibleForTailCallOptimization(SDValue Callee, 990203954Srdivacky CallingConv::ID CalleeCC, 991203954Srdivacky bool isVarArg, 992205218Srdivacky bool isCalleeStructRet, 993205218Srdivacky bool isCallerStructRet, 994243830Sdim Type *RetTy, 995203954Srdivacky const SmallVectorImpl<ISD::OutputArg> &Outs, 996210299Sed const SmallVectorImpl<SDValue> &OutVals, 997203954Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 998203954Srdivacky SelectionDAG& DAG) const; 999193323Sed SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr, 1000193323Sed SDValue Chain, bool IsTailCall, bool Is64Bit, 1001261991Sdim int FPDiff, SDLoc dl) const; 1002193323Sed 1003207618Srdivacky unsigned GetAlignedArgumentStackSize(unsigned StackSize, 1004207618Srdivacky SelectionDAG &DAG) const; 1005193323Sed 1006193323Sed std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, 1007234353Sdim bool isSigned, 1008234353Sdim bool isReplace) const; 1009200581Srdivacky 1010207618Srdivacky SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; 1011261991Sdim SDValue LowerBUILD_VECTORvXi1(SDValue Op, SelectionDAG &DAG) const; 1012276479Sdim SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const; 1013207618Srdivacky SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1014276479Sdim SDValue ExtractBitFromMaskVector(SDValue Op, SelectionDAG &DAG) const; 1015276479Sdim SDValue InsertBitToMaskVector(SDValue Op, SelectionDAG &DAG) const; 1016276479Sdim 1017207618Srdivacky SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; 1018207618Srdivacky SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; 1019207618Srdivacky SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 1020261991Sdim SDValue LowerGlobalAddress(const GlobalValue *GV, SDLoc dl, 1021193323Sed int64_t Offset, SelectionDAG &DAG) const; 1022207618Srdivacky SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; 1023207618Srdivacky SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 1024207618Srdivacky SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const; 1025207618Srdivacky SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1026207618Srdivacky SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const; 1027207618Srdivacky SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const; 1028207618Srdivacky SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const; 1029243830Sdim SDValue lowerUINT_TO_FP_vec(SDValue Op, SelectionDAG &DAG) const; 1030249423Sdim SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const; 1031207618Srdivacky SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const; 1032207618Srdivacky SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const; 1033207618Srdivacky SDValue LowerToBT(SDValue And, ISD::CondCode CC, 1034261991Sdim SDLoc dl, SelectionDAG &DAG) const; 1035207618Srdivacky SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; 1036296417Sdim SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const; 1037207618Srdivacky SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 1038207618Srdivacky SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const; 1039207618Srdivacky SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const; 1040207618Srdivacky SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 1041207618Srdivacky SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; 1042207618Srdivacky SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const; 1043207618Srdivacky SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 1044207618Srdivacky SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 1045207618Srdivacky SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const; 1046207618Srdivacky SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const; 1047243830Sdim SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 1048243830Sdim SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 1049226633Sdim SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; 1050207618Srdivacky SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 1051276479Sdim SDValue LowerWin64_i128OP(SDValue Op, SelectionDAG &DAG) const; 1052288943Sdim SDValue LowerGC_TRANSITION_START(SDValue Op, SelectionDAG &DAG) const; 1053288943Sdim SDValue LowerGC_TRANSITION_END(SDValue Op, SelectionDAG &DAG) const; 1054193323Sed 1055276479Sdim SDValue 1056198090Srdivacky LowerFormalArguments(SDValue Chain, 1057198090Srdivacky CallingConv::ID CallConv, bool isVarArg, 1058198090Srdivacky const SmallVectorImpl<ISD::InputArg> &Ins, 1059261991Sdim SDLoc dl, SelectionDAG &DAG, 1060276479Sdim SmallVectorImpl<SDValue> &InVals) const override; 1061276479Sdim SDValue LowerCall(CallLoweringInfo &CLI, 1062276479Sdim SmallVectorImpl<SDValue> &InVals) const override; 1063198090Srdivacky 1064276479Sdim SDValue LowerReturn(SDValue Chain, 1065276479Sdim CallingConv::ID CallConv, bool isVarArg, 1066276479Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 1067276479Sdim const SmallVectorImpl<SDValue> &OutVals, 1068276479Sdim SDLoc dl, SelectionDAG &DAG) const override; 1069198090Srdivacky 1070296417Sdim bool supportSplitCSR(MachineFunction *MF) const override { 1071296417Sdim return MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS && 1072296417Sdim MF->getFunction()->hasFnAttribute(Attribute::NoUnwind); 1073296417Sdim } 1074296417Sdim void initializeSplitCSR(MachineBasicBlock *Entry) const override; 1075296417Sdim void insertCopiesSplitCSR( 1076296417Sdim MachineBasicBlock *Entry, 1077296417Sdim const SmallVectorImpl<MachineBasicBlock *> &Exits) const override; 1078296417Sdim 1079276479Sdim bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 1080218893Sdim 1081276479Sdim bool mayBeEmittedAsTailCall(CallInst *CI) const override; 1082221345Sdim 1083280031Sdim EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1084276479Sdim ISD::NodeType ExtendKind) const override; 1085221345Sdim 1086276479Sdim bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, 1087276479Sdim bool isVarArg, 1088276479Sdim const SmallVectorImpl<ISD::OutputArg> &Outs, 1089276479Sdim LLVMContext &Context) const override; 1090199481Srdivacky 1091276479Sdim const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override; 1092261991Sdim 1093296417Sdim TargetLoweringBase::AtomicExpansionKind 1094296417Sdim shouldExpandAtomicLoadInIR(LoadInst *SI) const override; 1095280031Sdim bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override; 1096296417Sdim TargetLoweringBase::AtomicExpansionKind 1097288943Sdim shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override; 1098280031Sdim 1099280031Sdim LoadInst * 1100280031Sdim lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const override; 1101280031Sdim 1102296417Sdim bool needsCmpXchgNb(Type *MemType) const; 1103280031Sdim 1104218893Sdim // Utility function to emit the low-level va_arg code for X86-64. 1105218893Sdim MachineBasicBlock *EmitVAARG64WithCustomInserter( 1106218893Sdim MachineInstr *MI, 1107218893Sdim MachineBasicBlock *MBB) const; 1108218893Sdim 1109198090Srdivacky /// Utility function to emit the xmm reg save portion of va_start. 1110198090Srdivacky MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter( 1111198090Srdivacky MachineInstr *BInstr, 1112198090Srdivacky MachineBasicBlock *BB) const; 1113198090Srdivacky 1114198090Srdivacky MachineBasicBlock *EmitLoweredSelect(MachineInstr *I, 1115207618Srdivacky MachineBasicBlock *BB) const; 1116204961Srdivacky 1117296417Sdim MachineBasicBlock *EmitLoweredAtomicFP(MachineInstr *I, 1118296417Sdim MachineBasicBlock *BB) const; 1119296417Sdim 1120218893Sdim MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI, 1121207618Srdivacky MachineBasicBlock *BB) const; 1122218893Sdim 1123296417Sdim MachineBasicBlock *EmitLoweredCatchRet(MachineInstr *MI, 1124296417Sdim MachineBasicBlock *BB) const; 1125296417Sdim 1126296417Sdim MachineBasicBlock *EmitLoweredCatchPad(MachineInstr *MI, 1127296417Sdim MachineBasicBlock *BB) const; 1128296417Sdim 1129226633Sdim MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI, 1130280031Sdim MachineBasicBlock *BB) const; 1131226633Sdim 1132296417Sdim MachineBasicBlock *EmitLoweredTLSAddr(MachineInstr *MI, 1133210299Sed MachineBasicBlock *BB) const; 1134204961Srdivacky 1135296417Sdim MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, 1136218893Sdim MachineBasicBlock *BB) const; 1137218893Sdim 1138243830Sdim MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI, 1139243830Sdim MachineBasicBlock *MBB) const; 1140243830Sdim 1141243830Sdim MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI, 1142243830Sdim MachineBasicBlock *MBB) const; 1143243830Sdim 1144276479Sdim MachineBasicBlock *emitFMA3Instr(MachineInstr *MI, 1145276479Sdim MachineBasicBlock *MBB) const; 1146276479Sdim 1147193323Sed /// Emit nodes that will be selected as "test Op0,Op0", or something 1148193323Sed /// equivalent, for use with the given x86 condition code. 1149276479Sdim SDValue EmitTest(SDValue Op0, unsigned X86CC, SDLoc dl, 1150276479Sdim SelectionDAG &DAG) const; 1151193323Sed 1152193323Sed /// Emit nodes that will be selected as "cmp Op0,Op1", or something 1153193323Sed /// equivalent, for use with the given x86 condition code. 1154276479Sdim SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, SDLoc dl, 1155207618Srdivacky SelectionDAG &DAG) const; 1156239462Sdim 1157239462Sdim /// Convert a comparison if required by the subtarget. 1158239462Sdim SDValue ConvertCmpIfNecessary(SDValue Cmp, SelectionDAG &DAG) const; 1159280031Sdim 1160280031Sdim /// Use rsqrt* to speed up sqrt calculations. 1161280031Sdim SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI, 1162280031Sdim unsigned &RefinementSteps, 1163280031Sdim bool &UseOneConstNR) const override; 1164280031Sdim 1165280031Sdim /// Use rcp* to speed up fdiv calculations. 1166280031Sdim SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI, 1167280031Sdim unsigned &RefinementSteps) const override; 1168288943Sdim 1169288943Sdim /// Reassociate floating point divisions into multiply by reciprocal. 1170296417Sdim unsigned combineRepeatedFPDivisors() const override; 1171193323Sed }; 1172193323Sed 1173193323Sed namespace X86 { 1174239462Sdim FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 1175239462Sdim const TargetLibraryInfo *libInfo); 1176193323Sed } 1177193323Sed} 1178193323Sed 1179193323Sed#endif // X86ISELLOWERING_H 1180