Searched refs:reg (Results 676 - 700 of 1755) sorted by relevance

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/freebsd-11-stable/sys/dev/mii/
H A Dsmcphy.c128 int reg; local
155 reg = PHY_READ(sc, MII_BMCR);
156 if (reg & BMCR_ISO) {
157 PHY_WRITE(sc, MII_BMCR, reg & ~BMCR_ISO);
160 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
161 if (reg & BMSR_LINK) {
/freebsd-11-stable/sys/dev/netfpga10g/nf10bmac/
H A Dif_nf10bmac.c131 nf10bmac_write(struct resource *res, REGWTYPE reg, REGWTYPE val, argument
136 bus_write_8(res, reg, htole64(val));
138 bus_write_4(res, reg, htole32(val));
143 nf10bmac_read(struct resource *res, REGWTYPE reg, argument
148 return (le64toh(bus_read_8(res, reg)));
150 return (le32toh(bus_read_4(res, reg)));
155 nf10bmac_write_be(struct resource *res, REGWTYPE reg, REGWTYPE val, argument
160 bus_write_8(res, reg, htobe64(val));
162 bus_write_4(res, reg, htobe32(val));
168 nf10bmac_read_be(struct resource *res, REGWTYPE reg, argument
[all...]
/freebsd-11-stable/sys/powerpc/powermac/
H A Dpmu.c342 uint8_t reg; local
384 reg = PMU_DEFAULTS;
385 pmu_send(sc, PMU_SET_IMASK, 1, &reg, 16, resp);
646 uint8_t reg; local
648 reg = pmu_read_reg(sc, vACR);
649 reg &= ~vSR_OUT;
650 reg |= 0x0c;
651 pmu_write_reg(sc, vACR, reg);
657 uint8_t reg; local
659 reg
668 uint8_t reg; local
678 uint8_t reg; local
876 uint8_t reg; local
[all...]
/freebsd-11-stable/sys/powerpc/pseries/
H A Drtas_pci.c131 if (OF_getencprop(ofw_bus_get_node(dev), "reg", (pcell_t *)&sc->sc_pcir,
148 rtaspci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, argument
159 ((func & 0x7) << 8) | (reg & 0xff);
161 config_addr |= (reg & 0xf00) << 16;
189 u_int reg, uint32_t val, int width)
198 ((func & 0x7) << 8) | (reg & 0xff);
200 config_addr |= (reg & 0xf00) << 16;
188 rtaspci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, uint32_t val, int width) argument
/freebsd-11-stable/sys/sparc64/sparc64/
H A Djbusppm.c72 #define JBUSPPM_READ(sc, reg, off) \
73 bus_space_read_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off))
74 #define JBUSPPM_WRITE(sc, reg, off, val) \
75 bus_space_write_8((sc)->sc_bt[(reg)], (sc)->sc_bh[(reg)], (off), (val))
/freebsd-11-stable/sys/mips/mips/
H A Docteon_cop2_swtch.S37 #define SAVE_COP2_REGISTER(reg) \
38 dmfc2 t1, reg; sd t1, reg##_OFFSET(a0)
41 #define RESTORE_COP2_REGISTER(reg) \
42 ld t1, reg##_OFFSET(a0); dmtc2 t1, reg##_SET
/freebsd-11-stable/sys/dev/drm2/radeon/
H A Devergreen_cs.c1046 pkt->reg = CP_PACKET0_GET_REG(header);
1139 * PACKET3 - WAIT_REG_MEM poll vline status reg
1155 uint32_t header, h_idx, reg, wait_reg_mem_info; local
1173 /* bit 4 is reg (0) or mem (1) */
1184 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");
1204 reg = CP_PACKET0_GET_REG(header);
1224 switch (reg) {
1241 unsigned idx, unsigned reg)
1245 switch (reg) {
1250 idx, reg);
1239 evergreen_packet0_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt, unsigned idx, unsigned reg) argument
1265 unsigned reg, i; local
1290 evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) argument
1962 evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) argument
1996 unsigned start_reg, end_reg, reg; local
3319 evergreen_vm_reg_valid(u32 reg) argument
3446 u32 start_reg, end_reg, reg, i; local
[all...]
/freebsd-11-stable/sys/dev/extres/clk/
H A Dclk_div.c86 uint32_t reg; local
94 rv = RD4(clk, sc->offset, &reg);
99 i_div = (reg >> sc->i_shift) & sc->i_mask;
102 f_div = (reg >> sc->f_shift) & sc->f_mask;
130 uint32_t reg, i_div, f_div, hw_i_div; local
188 RD4(clk, sc->offset, &reg);
/freebsd-11-stable/sys/dev/sound/pci/
H A Dvibes.c121 sv_direct_get(struct sc_info *sc, u_int8_t reg) argument
123 return bus_space_read_1(sc->enh_st, sc->enh_sh, reg);
127 _sv_direct_set(struct sc_info *sc, u_int8_t reg, u_int8_t val, int line) argument
130 bus_space_write_1(sc->enh_st, sc->enh_sh, reg, val);
132 n = sv_direct_get(sc, reg);
134 device_printf(sc->dev, "sv_direct_set register 0x%02x %d != %d from line %d\n", reg, n, val, line);
139 sv_indirect_get(struct sc_info *sc, u_int8_t reg) argument
141 if (reg == SV_REG_FORMAT || reg == SV_REG_ANALOG_PWR)
142 reg |
151 _sv_indirect_set(struct sc_info *sc, u_int8_t reg, u_int8_t val, int line) argument
462 u_int8_t reg; /* Register */ member in struct:sv_mix_props
[all...]
H A Demu10kx-midi.c62 int port; /* I/O port or I/O ptr reg */
72 emu_mread(struct mpu401 *arg __unused, void *cookie, int reg) argument
79 d = emu_rd(sc->card, 0x18 + reg, 1);
81 d = emu_rdptr(sc->card, 0, sc->port + reg);
87 emu_mwrite(struct mpu401 *arg __unused, void *cookie, int reg, unsigned char b) argument
92 emu_wr(sc->card, 0x18 + reg, b, 1);
94 emu_wrptr(sc->card, 0, sc->port + reg, b);
H A Dcsamidi.c112 csamidi_mread(struct mpu401 *arg __unused, void *cookie, int reg) argument
120 switch (reg) {
132 printf("csamidi_mread: unknown register %d\n", reg);
139 csamidi_mwrite(struct mpu401 *arg __unused, void *cookie, int reg, unsigned char b) argument
144 switch (reg) {
169 printf("csamidi_mwrite: unknown register %d\n", reg);
/freebsd-11-stable/sys/arm/amlogic/aml8726/
H A Daml8726_wdt.c100 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
101 #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
102 #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
/freebsd-11-stable/lib/libkvm/
H A Dkvm_sparc64.c116 struct sparc64_dump_reg *reg, key; local
120 reg = bsearch(&key, vm->vm_regions, vm->vm_nregions,
122 if (reg == NULL)
124 o = pa - reg->dr_pa;
125 if (o + size > reg->dr_size)
127 return (reg->dr_offs + o);
/freebsd-11-stable/contrib/wpa/src/wps/
H A Dwps_i.h209 int wps_device_store(struct wps_registrar *reg,
211 void wps_registrar_selected_registrar_changed(struct wps_registrar *reg,
213 const u8 * wps_authorized_macs(struct wps_registrar *reg, size_t *count);
214 int wps_registrar_pbc_overlap(struct wps_registrar *reg,
216 void wps_registrar_remove_nfc_pw_token(struct wps_registrar *reg,
218 int wps_cb_new_psk(struct wps_registrar *reg, const u8 *mac_addr,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/MC/
H A DMCWin64EH.cpp334 uint8_t b, reg; local
389 assert(inst.Register >= 19 && "Saved reg must be >= 19");
390 reg = inst.Register - 19;
391 b = 0xD0 | ((reg & 0xC) >> 2);
393 b = ((reg & 0x3) << 6) | (inst.Offset >> 3);
397 assert(inst.Register >= 19 && "Saved reg must be >= 19");
398 reg = inst.Register - 19;
399 b = 0xD4 | ((reg & 0x8) >> 3);
401 b = ((reg & 0x7) << 5) | ((inst.Offset >> 3) - 1);
406 reg
[all...]
/freebsd-11-stable/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DDWARFLocationExpression.cpp132 llvm::codeview::RegisterId reg, llvm::Optional<int32_t> relative_offset,
137 module->GetArchitecture().GetMachine(), reg, register_kind);
162 llvm::codeview::RegisterId reg, lldb::ModuleSP module) {
163 return MakeRegisterBasedLocationExpressionInternal(reg, llvm::None, module);
167 llvm::codeview::RegisterId reg, int32_t offset, lldb::ModuleSP module) {
168 return MakeRegisterBasedLocationExpressionInternal(reg, offset, module);
131 MakeRegisterBasedLocationExpressionInternal( llvm::codeview::RegisterId reg, llvm::Optional<int32_t> relative_offset, lldb::ModuleSP module) argument
/freebsd-11-stable/sys/dev/msk/
H A Dif_mskreg.h433 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
456 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */
457 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */
458 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */
459 #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */
807 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
1047 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
1660 * Note: NA reg = Network Address e.g DA, SA etc.
2123 #define CSR_WRITE_4(sc, reg, val) \
2124 bus_write_4((sc)->msk_res[0], (reg), (va
[all...]
/freebsd-11-stable/sys/dev/ath/ath_hal/ar5211/
H A Dar5211_misc.c197 uint32_t reg; local
201 reg = OS_REG_READ(ah, AR_GPIOCR);
202 reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
203 reg |= AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT);
205 OS_REG_WRITE(ah, AR_GPIOCR, reg);
215 uint32_t reg; local
219 reg = OS_REG_READ(ah, AR_GPIOCR);
220 reg &= ~(AR_GPIOCR_0_CR_A << (gpio * AR_GPIOCR_CR_SHIFT));
221 reg |= AR_GPIOCR_0_CR_N << (gpio * AR_GPIOCR_CR_SHIFT);
223 OS_REG_WRITE(ah, AR_GPIOCR, reg);
233 uint32_t reg; local
[all...]
/freebsd-11-stable/sys/dev/iicbus/
H A Dad7417.c75 uint8_t reg; member in struct:write_data
80 uint8_t reg; member in struct:read_data
90 static int ad7417_write(device_t dev, uint32_t addr, uint8_t reg,
92 static int ad7417_read_1(device_t dev, uint32_t addr, uint8_t reg,
94 static int ad7417_read_2(device_t dev, uint32_t addr, uint8_t reg,
129 ad7417_write(device_t dev, uint32_t addr, uint8_t reg, uint8_t *buff, int len) argument
139 buf[0] = reg;
156 ad7417_read_1(device_t dev, uint32_t addr, uint8_t reg, uint8_t *data) argument
162 { addr, IIC_M_WR | IIC_M_NOSTOP, 1, &reg },
184 ad7417_read_2(device_t dev, uint32_t addr, uint8_t reg, uint16_ argument
[all...]
/freebsd-11-stable/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_misc.c369 u_int32_t reg; local
388 reg = OS_REG_READ(ah, AR_STA_ID1);
390 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
392 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
639 /* TSF shouldn't count twice or reg access is taking forever */
1313 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; local
1413 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW);
1415 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW),
1416 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW));
1417 reg
2635 ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) argument
2640 ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) argument
[all...]
/freebsd-11-stable/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_per.c554 uint32_t reg; local
561 RD4(sc, sc->base_reg, &reg);
566 sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;
570 sc->divider = (reg & sc->div_mask) + 2;
574 if (!(reg & PERLCK_UDIV_DIS))
580 if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {
582 ((reg >> PERLCK_AMUX_SHIFT) & PERLCK_MUX_MASK);
593 uint32_t reg; local
602 RD4(sc, sc->base_reg, &reg);
603 reg
627 uint32_t reg; local
761 uint32_t reg, mask, base_reg; local
780 uint32_t reg, mask, reset_reg; local
[all...]
/freebsd-11-stable/sys/arm/nvidia/
H A Dtegra_gpio.c150 gpio_write_masked(struct tegra_gpio_softc *sc, bus_size_t reg, argument
159 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin), tmp);
163 gpio_read(struct tegra_gpio_softc *sc, bus_size_t reg, struct gpio_pin *pin) argument
169 val = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(pin->gp_pin));
342 intr_write_masked(struct tegra_gpio_softc *sc, bus_addr_t reg, argument
351 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
355 intr_write_modify(struct tegra_gpio_softc *sc, bus_addr_t reg, argument
363 tmp = bus_read_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq));
366 bus_write_4(sc->mem_res, reg + GPIO_REGNUM(tgi->irq), tmp);
501 uint32_t reg; local
545 uint32_t reg; local
[all...]
/freebsd-11-stable/usr.sbin/fwcontrol/
H A Dfwcontrol.c336 u_int32_t max, reg, old; local
348 reg = read_write_quad(fd, devinfo->eui, BUGET_REG, 1, 0);
352 devinfo->dst, addr, reg);
353 if (reg > 0) {
354 old = (reg & 0x3f);
355 max = (reg & 0x3f00) >> 8;
428 struct csrreg *reg; local
441 reg = (struct csrreg *)hdr;
442 printf("verndor ID: 0x%06x\n", reg->val);
471 reg
561 struct fw_reg_req_t reg; local
577 struct fw_reg_req_t reg; local
[all...]
/freebsd-11-stable/sys/dev/ntb/ntb_hw/
H A Dntb_hw_plx.c120 #define NTX_READ(sc, reg) \
121 bus_read_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg))
122 #define NTX_WRITE(sc, reg, val) \
123 bus_write_4((sc)->conf_res, PLX_NTX_OUR_BASE(sc) + (reg), (val))
126 #define PNTX_READ(sc, reg) \
127 bus_read_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg))
128 #define PNTX_WRITE(sc, reg, val) \
129 bus_write_4((sc)->conf_res, PLX_NTX_PEER_BASE(sc) + (reg), (val))
132 #define BNTX_READ(sc, reg) \
134 PLX_NTX_BASE(sc) + (reg))
514 uint32_t reg, val; local
538 uint32_t reg, val; local
555 uint32_t reg, val; local
[all...]
/freebsd-11-stable/sys/arm64/arm64/
H A Dgicv3_its.c278 #define gic_its_read_4(sc, reg) \
279 bus_read_4((sc)->sc_its_res, (reg))
280 #define gic_its_read_8(sc, reg) \
281 bus_read_8((sc)->sc_its_res, (reg))
283 #define gic_its_write_4(sc, reg, val) \
284 bus_write_4((sc)->sc_its_res, (reg), (val))
285 #define gic_its_write_8(sc, reg, val) \
286 bus_write_8((sc)->sc_its_res, (reg), (val))
350 uint64_t reg, tmp; local
360 reg
397 uint64_t cache, reg, share, tmp, type; local
[all...]

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