1165138Syongari/****************************************************************************** 2165138Syongari * 3165138Syongari * Name: skgehw.h 4165138Syongari * Project: Gigabit Ethernet Adapters, Common Modules 5165138Syongari * Version: $Revision: 2.49 $ 6165138Syongari * Date: $Date: 2005/01/20 13:01:35 $ 7165138Syongari * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family 8165138Syongari * 9165138Syongari ******************************************************************************/ 10165138Syongari 11165138Syongari/****************************************************************************** 12165138Syongari * 13165138Syongari * LICENSE: 14165138Syongari * Copyright (C) Marvell International Ltd. and/or its affiliates 15165138Syongari * 16165138Syongari * The computer program files contained in this folder ("Files") 17165138Syongari * are provided to you under the BSD-type license terms provided 18165138Syongari * below, and any use of such Files and any derivative works 19165138Syongari * thereof created by you shall be governed by the following terms 20165138Syongari * and conditions: 21165138Syongari * 22165138Syongari * - Redistributions of source code must retain the above copyright 23165138Syongari * notice, this list of conditions and the following disclaimer. 24165138Syongari * - Redistributions in binary form must reproduce the above 25165138Syongari * copyright notice, this list of conditions and the following 26165138Syongari * disclaimer in the documentation and/or other materials provided 27165138Syongari * with the distribution. 28165138Syongari * - Neither the name of Marvell nor the names of its contributors 29165138Syongari * may be used to endorse or promote products derived from this 30165138Syongari * software without specific prior written permission. 31165138Syongari * 32165138Syongari * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33165138Syongari * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34165138Syongari * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35165138Syongari * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36165138Syongari * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37165138Syongari * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38165138Syongari * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39165138Syongari * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40165138Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41165138Syongari * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42165138Syongari * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43165138Syongari * OF THE POSSIBILITY OF SUCH DAMAGE. 44165138Syongari * /LICENSE 45165138Syongari * 46165138Syongari ******************************************************************************/ 47165138Syongari 48165138Syongari/*- 49165138Syongari * Copyright (c) 1997, 1998, 1999, 2000 50165138Syongari * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51165138Syongari * 52165138Syongari * Redistribution and use in source and binary forms, with or without 53165138Syongari * modification, are permitted provided that the following conditions 54165138Syongari * are met: 55165138Syongari * 1. Redistributions of source code must retain the above copyright 56165138Syongari * notice, this list of conditions and the following disclaimer. 57165138Syongari * 2. Redistributions in binary form must reproduce the above copyright 58165138Syongari * notice, this list of conditions and the following disclaimer in the 59165138Syongari * documentation and/or other materials provided with the distribution. 60165138Syongari * 3. All advertising materials mentioning features or use of this software 61165138Syongari * must display the following acknowledgement: 62165138Syongari * This product includes software developed by Bill Paul. 63165138Syongari * 4. Neither the name of the author nor the names of any co-contributors 64165138Syongari * may be used to endorse or promote products derived from this software 65165138Syongari * without specific prior written permission. 66165138Syongari * 67165138Syongari * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68165138Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69165138Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70165138Syongari * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71165138Syongari * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72165138Syongari * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73165138Syongari * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74165138Syongari * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75165138Syongari * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76165138Syongari * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77165138Syongari * THE POSSIBILITY OF SUCH DAMAGE. 78165138Syongari */ 79165138Syongari 80165138Syongari/*- 81165138Syongari * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 82165138Syongari * 83165138Syongari * Permission to use, copy, modify, and distribute this software for any 84165138Syongari * purpose with or without fee is hereby granted, provided that the above 85165138Syongari * copyright notice and this permission notice appear in all copies. 86165138Syongari * 87165138Syongari * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 88165138Syongari * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 89165138Syongari * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 90165138Syongari * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 91165138Syongari * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 92165138Syongari * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 93165138Syongari * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 94165138Syongari */ 95165138Syongari 96165138Syongari/*$FreeBSD$*/ 97165138Syongari 98165138Syongari/* 99165138Syongari * SysKonnect PCI vendor ID 100165138Syongari */ 101165138Syongari#define VENDORID_SK 0x1148 102165138Syongari 103165138Syongari/* 104165138Syongari * Marvell PCI vendor ID 105165138Syongari */ 106165138Syongari#define VENDORID_MARVELL 0x11AB 107165138Syongari 108165138Syongari/* 109165138Syongari * D-Link PCI vendor ID 110165138Syongari */ 111165138Syongari#define VENDORID_DLINK 0x1186 112165138Syongari 113165138Syongari/* 114165138Syongari * SysKonnect ethernet device IDs 115165138Syongari */ 116165138Syongari#define DEVICEID_SK_YUKON2 0x9000 117165138Syongari#define DEVICEID_SK_YUKON2_EXPR 0x9e00 118165138Syongari 119165138Syongari/* 120165138Syongari * Marvell gigabit ethernet device IDs 121165138Syongari */ 122165138Syongari#define DEVICEID_MRVL_8021CU 0x4340 123165138Syongari#define DEVICEID_MRVL_8022CU 0x4341 124165138Syongari#define DEVICEID_MRVL_8061CU 0x4342 125165138Syongari#define DEVICEID_MRVL_8062CU 0x4343 126165138Syongari#define DEVICEID_MRVL_8021X 0x4344 127165138Syongari#define DEVICEID_MRVL_8022X 0x4345 128165138Syongari#define DEVICEID_MRVL_8061X 0x4346 129165138Syongari#define DEVICEID_MRVL_8062X 0x4347 130165138Syongari#define DEVICEID_MRVL_8035 0x4350 131165138Syongari#define DEVICEID_MRVL_8036 0x4351 132165138Syongari#define DEVICEID_MRVL_8038 0x4352 133192736Syongari#define DEVICEID_MRVL_8039 0x4353 134192736Syongari#define DEVICEID_MRVL_8040 0x4354 135192736Syongari#define DEVICEID_MRVL_8040T 0x4355 136198475Slulf#define DEVICEID_MRVL_8042 0x4357 137192736Syongari#define DEVICEID_MRVL_8048 0x435A 138165138Syongari#define DEVICEID_MRVL_4360 0x4360 139165138Syongari#define DEVICEID_MRVL_4361 0x4361 140165138Syongari#define DEVICEID_MRVL_4362 0x4362 141165138Syongari#define DEVICEID_MRVL_4363 0x4363 142165138Syongari#define DEVICEID_MRVL_4364 0x4364 143193299Syongari#define DEVICEID_MRVL_4365 0x4365 144173775Syongari#define DEVICEID_MRVL_436A 0x436A 145193299Syongari#define DEVICEID_MRVL_436B 0x436B 146193299Syongari#define DEVICEID_MRVL_436C 0x436C 147222230Syongari#define DEVICEID_MRVL_436D 0x436D 148222230Syongari#define DEVICEID_MRVL_4370 0x4370 149199012Syongari#define DEVICEID_MRVL_4380 0x4380 150207445Syongari#define DEVICEID_MRVL_4381 0x4381 151165138Syongari 152165138Syongari/* 153165138Syongari * D-Link gigabit ethernet device ID 154165138Syongari */ 155165138Syongari#define DEVICEID_DLINK_DGE550SX 0x4001 156197592Syongari#define DEVICEID_DLINK_DGE560SX 0x4002 157165138Syongari#define DEVICEID_DLINK_DGE560T 0x4b00 158165138Syongari 159258780Seadler#define BIT_31 (1U << 31) 160165138Syongari#define BIT_30 (1 << 30) 161165138Syongari#define BIT_29 (1 << 29) 162165138Syongari#define BIT_28 (1 << 28) 163165138Syongari#define BIT_27 (1 << 27) 164165138Syongari#define BIT_26 (1 << 26) 165165138Syongari#define BIT_25 (1 << 25) 166165138Syongari#define BIT_24 (1 << 24) 167165138Syongari#define BIT_23 (1 << 23) 168165138Syongari#define BIT_22 (1 << 22) 169165138Syongari#define BIT_21 (1 << 21) 170165138Syongari#define BIT_20 (1 << 20) 171165138Syongari#define BIT_19 (1 << 19) 172165138Syongari#define BIT_18 (1 << 18) 173165138Syongari#define BIT_17 (1 << 17) 174165138Syongari#define BIT_16 (1 << 16) 175165138Syongari#define BIT_15 (1 << 15) 176165138Syongari#define BIT_14 (1 << 14) 177165138Syongari#define BIT_13 (1 << 13) 178165138Syongari#define BIT_12 (1 << 12) 179165138Syongari#define BIT_11 (1 << 11) 180165138Syongari#define BIT_10 (1 << 10) 181165138Syongari#define BIT_9 (1 << 9) 182165138Syongari#define BIT_8 (1 << 8) 183165138Syongari#define BIT_7 (1 << 7) 184165138Syongari#define BIT_6 (1 << 6) 185165138Syongari#define BIT_5 (1 << 5) 186165138Syongari#define BIT_4 (1 << 4) 187165138Syongari#define BIT_3 (1 << 3) 188165138Syongari#define BIT_2 (1 << 2) 189165138Syongari#define BIT_1 (1 << 1) 190165138Syongari#define BIT_0 (1 << 0) 191165138Syongari 192165138Syongari#define SHIFT31(x) ((x) << 31) 193165138Syongari#define SHIFT30(x) ((x) << 30) 194165138Syongari#define SHIFT29(x) ((x) << 29) 195165138Syongari#define SHIFT28(x) ((x) << 28) 196165138Syongari#define SHIFT27(x) ((x) << 27) 197165138Syongari#define SHIFT26(x) ((x) << 26) 198165138Syongari#define SHIFT25(x) ((x) << 25) 199165138Syongari#define SHIFT24(x) ((x) << 24) 200165138Syongari#define SHIFT23(x) ((x) << 23) 201165138Syongari#define SHIFT22(x) ((x) << 22) 202165138Syongari#define SHIFT21(x) ((x) << 21) 203165138Syongari#define SHIFT20(x) ((x) << 20) 204165138Syongari#define SHIFT19(x) ((x) << 19) 205165138Syongari#define SHIFT18(x) ((x) << 18) 206165138Syongari#define SHIFT17(x) ((x) << 17) 207165138Syongari#define SHIFT16(x) ((x) << 16) 208165138Syongari#define SHIFT15(x) ((x) << 15) 209165138Syongari#define SHIFT14(x) ((x) << 14) 210165138Syongari#define SHIFT13(x) ((x) << 13) 211165138Syongari#define SHIFT12(x) ((x) << 12) 212165138Syongari#define SHIFT11(x) ((x) << 11) 213165138Syongari#define SHIFT10(x) ((x) << 10) 214165138Syongari#define SHIFT9(x) ((x) << 9) 215165138Syongari#define SHIFT8(x) ((x) << 8) 216165138Syongari#define SHIFT7(x) ((x) << 7) 217165138Syongari#define SHIFT6(x) ((x) << 6) 218165138Syongari#define SHIFT5(x) ((x) << 5) 219165138Syongari#define SHIFT4(x) ((x) << 4) 220165138Syongari#define SHIFT3(x) ((x) << 3) 221165138Syongari#define SHIFT2(x) ((x) << 2) 222165138Syongari#define SHIFT1(x) ((x) << 1) 223165138Syongari#define SHIFT0(x) ((x) << 0) 224165138Syongari 225165138Syongari/* 226165138Syongari * PCI Configuration Space header 227165138Syongari */ 228165138Syongari#define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 229165138Syongari#define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 230165138Syongari#define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ 231165138Syongari#define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ 232165138Syongari#define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ 233165138Syongari#define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ 234165138Syongari#define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ 235165138Syongari#define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ 236193293Syongari#define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ 237193293Syongari#define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ 238165138Syongari 239165138Syongari/* PCI Express Capability */ 240165138Syongari#define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ 241165138Syongari#define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ 242165138Syongari#define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ 243165138Syongari#define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ 244165138Syongari#define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ 245165138Syongari#define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ 246165138Syongari#define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ 247165138Syongari#define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ 248165138Syongari#define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ 249165138Syongari 250165138Syongari/* PCI Express Extended Capabilities */ 251165138Syongari#define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ 252165138Syongari#define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ 253165138Syongari#define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ 254165138Syongari#define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ 255165138Syongari#define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ 256165138Syongari#define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ 257165138Syongari#define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ 258165138Syongari#define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ 259165138Syongari 260165138Syongari/* PCI_OUR_REG_1 32 bit Our Register 1 */ 261165138Syongari#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ 262165138Syongari#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ 263165138Syongari#define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ 264165138Syongari#define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ 265165138Syongari#define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ 266165138Syongari#define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ 267165138Syongari#define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ 268165138Syongari#define PCI_EN_IO BIT_23 /* Mapping to I/O space */ 269165138Syongari#define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ 270165138Syongari /* 1 = Map Flash to memory */ 271165138Syongari /* 0 = Disable addr. dec */ 272165138Syongari#define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ 273165138Syongari#define PCI_PAGE_16 (0L<<20)/* 16 k pages */ 274165138Syongari#define PCI_PAGE_32K (1L<<20)/* 32 k pages */ 275165138Syongari#define PCI_PAGE_64K (2L<<20)/* 64 k pages */ 276165138Syongari#define PCI_PAGE_128K (3L<<20)/* 128 k pages */ 277165138Syongari#define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ 278165138Syongari#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ 279165138Syongari#define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ 280165138Syongari#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ 281165138Syongari#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ 282165138Syongari#define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ 283165138Syongari#define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ 284165138Syongari#define PCI_BURST_DIS BIT_9 /* Burst Disable */ 285165138Syongari#define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ 286165138Syongari#define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ 287165138Syongari#define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ 288165138Syongari#define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ 289165138Syongari 290165138Syongari/* PCI_OUR_REG_2 32 bit Our Register 2 */ 291165138Syongari#define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ 292165138Syongari#define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ 293165138Syongari#define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ 294165138Syongari /* Bit 13..12: reserved */ 295165138Syongari#define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ 296165138Syongari#define PCI_PATCH_DIR_3 BIT_11 297165138Syongari#define PCI_PATCH_DIR_2 BIT_10 298165138Syongari#define PCI_PATCH_DIR_1 BIT_9 299165138Syongari#define PCI_PATCH_DIR_0 BIT_8 300165138Syongari#define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ 301165138Syongari#define PCI_EXT_PATCH_3 BIT_7 302165138Syongari#define PCI_EXT_PATCH_2 BIT_6 303165138Syongari#define PCI_EXT_PATCH_1 BIT_5 304165138Syongari#define PCI_EXT_PATCH_0 BIT_4 305165138Syongari#define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ 306165138Syongari#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ 307165138Syongari#define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ 308165138Syongari 309165138Syongari/* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ 310165138Syongari#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ 311165138Syongari#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ 312165138Syongari#define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ 313165138Syongari#define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ 314165138Syongari#define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ 315165138Syongari#define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ 316165138Syongari#define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ 317165138Syongari#define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ 318165138Syongari 319165138Syongari#define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ 320165138Syongari/* possible values for the speed field of the register */ 321165138Syongari#define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ 322165138Syongari#define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ 323165138Syongari#define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ 324165138Syongari#define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ 325165138Syongari 326222230Syongari/* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */ 327222230Syongari#define PCI_CLK_MACSEC_DIS BIT_17 /* Disable Clock MACSec. */ 328222230Syongari 329165138Syongari/* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 330165138Syongari#define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ 331165138Syongari#define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ 332165138Syongari#define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ 333165138Syongari#define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ 334165138Syongari#define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ 335165138Syongari#define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ 336165138Syongari#define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ 337165138Syongari#define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ 338165138Syongari#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ 339165138Syongari#define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ 340165138Syongari 341193293Syongari/* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 342193293Syongari /* Bit 31..27: for A3 & later */ 343193293Syongari#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ 344193293Syongari#define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ 345193293Syongari#define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ 346193293Syongari#define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ 347193293Syongari#define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ 348193293Syongari#define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27) 349193293Syongari /* Bit 26..16: Release Clock on Event */ 350193293Syongari#define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ 351193293Syongari#define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ 352193293Syongari#define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ 353193293Syongari#define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ 354193293Syongari#define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ 355193293Syongari#define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ 356193293Syongari#define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ 357193293Syongari#define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ 358193293Syongari#define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ 359193293Syongari#define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ 360193293Syongari#define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ 361193293Syongari /* Bit 10.. 0: Mask for Gate Clock */ 362193293Syongari#define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ 363193293Syongari#define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ 364193293Syongari#define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ 365193293Syongari#define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ 366193293Syongari#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ 367193293Syongari#define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ 368193293Syongari#define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ 369193293Syongari#define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ 370193293Syongari#define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ 371193293Syongari#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ 372193293Syongari#define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ 373193293Syongari 374193293Syongari/* PCI_CFG_REG_1 32 bit Config Register 1 */ 375193293Syongari#define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ 376193293Syongari /* Bit 23..21: Release Clock on Event */ 377193293Syongari#define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ 378193293Syongari#define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ 379193293Syongari#define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ 380193293Syongari /* Bit 20..18: Gate Clock on Event */ 381193293Syongari#define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ 382193293Syongari#define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ 383193293Syongari#define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ 384193293Syongari#define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 385193293Syongari#define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ 386193293Syongari 387193293Syongari#define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ 388193293Syongari#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ 389193293Syongari#define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ 390193293Syongari 391165138Syongari/* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ 392165138Syongari#define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ 393165138Syongari#define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ 394165138Syongari#define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ 395165138Syongari#define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ 396165138Syongari#define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ 397165138Syongari#define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ 398165138Syongari#define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ 399165138Syongari#define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ 400165138Syongari#define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ 401165138Syongari#define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ 402165138Syongari#define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ 403165138Syongari 404165138Syongari#define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) 405165138Syongari 406165138Syongari/* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ 407165138Syongari#define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ 408165138Syongari#define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ 409165138Syongari#define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ 410165138Syongari#define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ 411165138Syongari#define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ 412165138Syongari 413165138Syongari/* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 414165138Syongari#define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ 415165138Syongari#define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ 416165138Syongari#define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ 417165138Syongari#define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ 418165138Syongari#define PEX_COMP_TO BIT_14 /* Completion Timeout */ 419165138Syongari#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ 420165138Syongari#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ 421165138Syongari#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ 422165138Syongari 423165138Syongari#define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) 424165138Syongari 425165138Syongari/* Control Register File (Address Map) */ 426165138Syongari 427165138Syongari/* 428165138Syongari * Bank 0 429165138Syongari */ 430165138Syongari#define B0_RAP 0x0000 /* 8 bit Register Address Port */ 431165138Syongari#define B0_CTST 0x0004 /* 16 bit Control/Status register */ 432165138Syongari#define B0_LED 0x0006 /* 8 Bit LED register */ 433165138Syongari#define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ 434165138Syongari#define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ 435165138Syongari#define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ 436165138Syongari#define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ 437165138Syongari#define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ 438165138Syongari#define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ 439165138Syongari 440165138Syongari/* Special ISR registers (Yukon-2 only) */ 441165138Syongari#define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ 442165138Syongari#define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ 443165138Syongari#define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ 444165138Syongari#define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ 445165138Syongari#define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ 446165138Syongari 447165138Syongari/* 448165138Syongari * Bank 1 449165138Syongari * - completely empty (this is the RAP Block window) 450165138Syongari * Note: if RAP = 1 this page is reserved 451165138Syongari */ 452165138Syongari 453165138Syongari/* 454165138Syongari * Bank 2 455165138Syongari */ 456165138Syongari/* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ 457165138Syongari#define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ 458165138Syongari#define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ 459165138Syongari#define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ 460165138Syongari#define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ 461165138Syongari#define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ 462165138Syongari#define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ 463165138Syongari#define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ 464165138Syongari#define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ 465165138Syongari#define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ 466165138Syongari#define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ 467165138Syongari#define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ 468165138Syongari#define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ 469165138Syongari#define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ 470165138Syongari#define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ 471165138Syongari#define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ 472165138Syongari#define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ 473165138Syongari#define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ 474165138Syongari#define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ 475165138Syongari#define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ 476165138Syongari#define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ 477165138Syongari#define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ 478165138Syongari#define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ 479165138Syongari#define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ 480165138Syongari#define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ 481165138Syongari#define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ 482165138Syongari#define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ 483165138Syongari#define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ 484165138Syongari#define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ 485165138Syongari#define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ 486165138Syongari 487165138Syongari#define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ 488165138Syongari#define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ 489165138Syongari 490165138Syongari/* 491165138Syongari * Bank 3 492165138Syongari */ 493165138Syongari/* RAM Random Registers */ 494165138Syongari#define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ 495165138Syongari#define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ 496165138Syongari#define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ 497165138Syongari 498165138Syongari#define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ 499165138Syongari 500165138Syongari/* RAM Interface Registers */ 501165138Syongari/* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ 502165138Syongari/* 503165138Syongari * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 504165138Syongari * not usable in SW. Please notice these are NOT real timeouts, these are 505165138Syongari * the number of qWords transferred continuously. 506165138Syongari */ 507165138Syongari#define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ 508165138Syongari#define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ 509165138Syongari#define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ 510165138Syongari#define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ 511165138Syongari#define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ 512165138Syongari#define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ 513165138Syongari#define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ 514165138Syongari#define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ 515165138Syongari#define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ 516165138Syongari#define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ 517165138Syongari#define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ 518165138Syongari#define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ 519165138Syongari#define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ 520165138Syongari#define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ 521165138Syongari#define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ 522165138Syongari 523165138Syongari/* 524165138Syongari * Bank 4 - 5 525165138Syongari */ 526165138Syongari/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 527165138Syongari#define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ 528165138Syongari#define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ 529165138Syongari#define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ 530165138Syongari#define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ 531165138Syongari#define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ 532165138Syongari#define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ 533165138Syongari#define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ 534165138Syongari 535165138Syongari#define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) 536165138Syongari 537165138Syongari/* RSS key registers for Yukon-2 Family */ 538165138Syongari#define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ 539165138Syongari/* RSS key register offsets */ 540165138Syongari#define KEY_IDX_0 0 /* offset for location of KEY 0 */ 541165138Syongari#define KEY_IDX_1 4 /* offset for location of KEY 1 */ 542165138Syongari#define KEY_IDX_2 8 /* offset for location of KEY 2 */ 543165138Syongari#define KEY_IDX_3 12 /* offset for location of KEY 3 */ 544165138Syongari /* 0x0280 - 0x0292: MAC 2 */ 545165138Syongari#define RSS_KEY_ADDR(Port, KeyIndex) \ 546165138Syongari ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) 547165138Syongari 548165138Syongari/* 549165138Syongari * Bank 8 - 15 550165138Syongari */ 551165138Syongari/* Receive and Transmit Queue Registers, use Q_ADDR() to access */ 552165138Syongari#define B8_Q_REGS 0x0400 553165138Syongari 554165138Syongari/* Queue Register Offsets, use Q_ADDR() to access */ 555165138Syongari#define Q_D 0x00 /* 8*32 bit Current Descriptor */ 556165138Syongari#define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ 557165138Syongari#define Q_DONE 0x24 /* 16 bit Done Index */ 558165138Syongari#define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ 559165138Syongari#define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ 560165138Syongari#define Q_BC 0x30 /* 32 bit Current Byte Counter */ 561165138Syongari#define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ 562165138Syongari#define Q_F 0x38 /* 32 bit Flag Register */ 563165138Syongari#define Q_T1 0x3c /* 32 bit Test Register 1 */ 564165138Syongari#define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ 565165138Syongari#define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ 566165138Syongari#define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ 567165138Syongari#define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ 568165138Syongari#define Q_WM 0x40 /* 16 bit FIFO Watermark */ 569165138Syongari#define Q_AL 0x42 /* 8 bit FIFO Alignment */ 570165138Syongari#define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ 571165138Syongari#define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ 572165138Syongari#define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ 573165138Syongari#define Q_RL 0x4a /* 8 bit FIFO Read Level */ 574165138Syongari#define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ 575165138Syongari#define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ 576165138Syongari#define Q_WL 0x4e /* 8 bit FIFO Write Level */ 577165138Syongari#define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ 578165138Syongari 579165138Syongari#define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) 580165138Syongari 581165138Syongari/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */ 582165138Syongari#define Y2_B8_PREF_REGS 0x0450 583165138Syongari 584165138Syongari#define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ 585165138Syongari#define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ 586165138Syongari#define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ 587165138Syongari#define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ 588165138Syongari#define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ 589165138Syongari#define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ 590165138Syongari#define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ 591165138Syongari#define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ 592165138Syongari#define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ 593165138Syongari#define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ 594165138Syongari 595165138Syongari#define PREF_UNIT_MASK_IDX 0x0fff 596165138Syongari 597165138Syongari#define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) 598165138Syongari 599165138Syongari/* 600165138Syongari * Bank 16 - 23 601165138Syongari */ 602165138Syongari/* RAM Buffer Registers */ 603165138Syongari#define B16_RAM_REGS 0x0800 604165138Syongari 605165138Syongari/* RAM Buffer Register Offsets, use RB_ADDR() to access */ 606165138Syongari#define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ 607165138Syongari#define RB_END 0x04 /* 32 bit RAM Buffer End Address */ 608165138Syongari#define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ 609165138Syongari#define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ 610165138Syongari#define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ 611165138Syongari#define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ 612165138Syongari#define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ 613165138Syongari#define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ 614165138Syongari#define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ 615165138Syongari#define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ 616165138Syongari#define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ 617165138Syongari#define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ 618165138Syongari#define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ 619165138Syongari 620165138Syongari/* 621165138Syongari * Bank 24 622165138Syongari */ 623165138Syongari/* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 624165138Syongari#define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ 625165138Syongari#define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 626165138Syongari#define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ 627165138Syongari#define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ 628165138Syongari#define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ 629165138Syongari#define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ 630207409Syongari#define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */ 631207409Syongari#define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */ 632165138Syongari#define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ 633165138Syongari#define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ 634165138Syongari#define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ 635165138Syongari#define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ 636165138Syongari#define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ 637165138Syongari 638165138Syongari/* 639165138Syongari * Bank 25 640165138Syongari */ 641165138Syongari /* 0x0c80 - 0x0cbf: MAC 2 */ 642165138Syongari /* 0x0cc0 - 0x0cff: reserved */ 643165138Syongari 644165138Syongari/* 645165138Syongari * Bank 26 646165138Syongari */ 647165138Syongari/* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 648165138Syongari#define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ 649165138Syongari#define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 650165138Syongari#define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ 651165138Syongari#define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ 652165138Syongari#define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ 653165138Syongari#define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ 654165138Syongari#define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ 655165138Syongari#define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ 656165138Syongari#define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ 657165138Syongari#define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ 658165138Syongari 659165138Syongari/* 660165138Syongari * Bank 27 661165138Syongari */ 662165138Syongari /* 0x0d80 - 0x0dbf: MAC 2 */ 663165138Syongari /* 0x0daa - 0x0dff: reserved */ 664165138Syongari 665165138Syongari/* 666165138Syongari * Bank 28 667165138Syongari */ 668165138Syongari/* Descriptor Poll Timer Registers */ 669165138Syongari#define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ 670165138Syongari#define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ 671165138Syongari#define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ 672165138Syongari#define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ 673165138Syongari/* Time Stamp Timer Registers (YUKON only) */ 674165138Syongari#define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ 675165138Syongari#define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ 676165138Syongari#define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ 677165138Syongari/* Polling Unit Registers (Yukon-2 only) */ 678165138Syongari#define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ 679165138Syongari#define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ 680165138Syongari#define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ 681165138Syongari#define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ 682165138Syongari/* ASF Subsystem Registers (Yukon-2 only) */ 683165138Syongari#define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ 684165138Syongari#define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ 685222227Syongari#define B28_Y2_CPU_WDOG 0x0e48 /* 32 bit Watchdog Register */ 686165138Syongari#define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ 687165138Syongari#define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ 688193293Syongari#define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ 689165138Syongari#define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ 690165138Syongari#define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ 691165138Syongari#define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ 692165138Syongari#define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ 693165138Syongari#define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ 694165138Syongari 695165138Syongari/* 696165138Syongari * Bank 29 697165138Syongari */ 698165138Syongari 699165138Syongari/* Status BMU Registers (Yukon-2 only)*/ 700165138Syongari#define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ 701165138Syongari#define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ 702165138Syongari#define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ 703165138Syongari#define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ 704165138Syongari#define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ 705165138Syongari#define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ 706165138Syongari#define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ 707165138Syongari#define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ 708165138Syongari#define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ 709165138Syongari#define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ 710165138Syongari/* FIFO Control/Status Registers (Yukon-2 only)*/ 711165138Syongari#define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ 712165138Syongari#define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ 713165138Syongari#define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ 714165138Syongari#define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ 715165138Syongari#define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ 716165138Syongari#define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ 717165138Syongari#define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ 718165138Syongari/* Level and ISR Timer Registers (Yukon-2 only)*/ 719165138Syongari#define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ 720165138Syongari#define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ 721165138Syongari#define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ 722165138Syongari#define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ 723165138Syongari#define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ 724165138Syongari#define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ 725165138Syongari#define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ 726165138Syongari#define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ 727165138Syongari#define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ 728165138Syongari#define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ 729165138Syongari#define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ 730165138Syongari#define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ 731165138Syongari 732165138Syongari#define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ 733165138Syongari#define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ 734165138Syongari#define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ 735165138Syongari#define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ 736165138Syongari 737165138Syongari/* 738165138Syongari * Bank 30 739165138Syongari */ 740165138Syongari/* GMAC and GPHY Control Registers (YUKON only) */ 741165138Syongari#define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ 742165138Syongari#define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ 743165138Syongari#define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ 744165138Syongari#define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ 745165138Syongari#define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ 746165138Syongari 747165138Syongari/* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 748165138Syongari 749165138Syongari#define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ 750165138Syongari 751165138Syongari#define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ 752165138Syongari#define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ 753165138Syongari#define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ 754165138Syongari#define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ 755165138Syongari#define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ 756165138Syongari#define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ 757165138Syongari#define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ 758165138Syongari#define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ 759165138Syongari 760165138Syongari/* WOL Pattern Length Registers (YUKON only) */ 761165138Syongari 762165138Syongari#define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ 763165138Syongari#define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ 764165138Syongari 765165138Syongari/* WOL Pattern Counter Registers (YUKON only) */ 766165138Syongari 767165138Syongari#define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ 768165138Syongari#define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ 769165138Syongari 770165138Syongari/* 771165138Syongari * Bank 32 - 33 772165138Syongari */ 773165138Syongari#define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ 774165138Syongari#define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ 775165138Syongari 776165138Syongari/* offset to configuration space on Yukon-2 */ 777165138Syongari#define Y2_CFG_SPC 0x1c00 778165138Syongari#define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ 779165138Syongari#define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ 780165138Syongari 781165138Syongari/* 782165138Syongari * Control Register Bit Definitions: 783165138Syongari */ 784165138Syongari/* B0_CTST 24 bit Control/Status register */ 785165138Syongari#define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ 786165138Syongari#define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ 787165138Syongari#define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ 788165138Syongari#define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ 789165138Syongari#define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ 790165138Syongari#define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ 791165138Syongari#define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ 792165138Syongari#define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ 793165138Syongari#define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ 794165138Syongari#define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ 795165138Syongari#define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ 796165138Syongari#define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ 797165138Syongari#define CS_STOP_DONE BIT_5 /* Stop Master is finished */ 798165138Syongari#define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ 799165138Syongari#define CS_MRST_CLR BIT_3 /* Clear Master Reset */ 800165138Syongari#define CS_MRST_SET BIT_2 /* Set Master Reset */ 801165138Syongari#define CS_RST_CLR BIT_1 /* Clear Software Reset */ 802165138Syongari#define CS_RST_SET BIT_0 /* Set Software Reset */ 803165138Syongari 804165138Syongari#define LED_STAT_ON BIT_1 /* Status LED On */ 805165138Syongari#define LED_STAT_OFF BIT_0 /* Status LED Off */ 806165138Syongari 807165138Syongari/* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 808165138Syongari#define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ 809165138Syongari#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ 810165138Syongari#define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ 811165138Syongari#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ 812165138Syongari#define PC_VAUX_ON BIT_3 /* Switch VAUX On */ 813165138Syongari#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ 814165138Syongari#define PC_VCC_ON BIT_1 /* Switch VCC On */ 815165138Syongari#define PC_VCC_OFF BIT_0 /* Switch VCC Off */ 816165138Syongari 817165138Syongari/* B0_ISRC 32 bit Interrupt Source Register */ 818165138Syongari/* B0_IMSK 32 bit Interrupt Mask Register */ 819165138Syongari/* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ 820165138Syongari/* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 821165138Syongari/* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 822165138Syongari/* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 823165138Syongari/* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 824165138Syongari/* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 825165138Syongari#define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) 826165138Syongari#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ 827165138Syongari#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ 828165138Syongari#define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ 829165138Syongari#define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ 830165138Syongari#define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ 831165138Syongari#define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ 832165138Syongari#define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ 833165138Syongari#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ 834165138Syongari#define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ 835165138Syongari#define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ 836165138Syongari#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ 837165138Syongari#define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ 838207445Syongari#define Y2_IS_PSM_ACK BIT_7 /* PSM Ack (Yukon Optima) */ 839207445Syongari#define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */ 840207445Syongari#define Y2_IS_PHY_QLNK BIT_5 /* PHY Quick Link (Yukon Optima) */ 841165138Syongari#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ 842165138Syongari#define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ 843165138Syongari#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ 844165138Syongari#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ 845165138Syongari#define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ 846165138Syongari 847165138Syongari#define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ 848165138Syongari 849165138Syongari#define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ 850165138Syongari 851165138Syongari#define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ 852165138Syongari 853165138Syongari#define Y2_IS_PORT_A \ 854165138Syongari (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) 855165138Syongari#define Y2_IS_PORT_B \ 856165138Syongari (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) 857165138Syongari 858165138Syongari/* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ 859165138Syongari/* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ 860165138Syongari/* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 861165138Syongari#define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ 862165138Syongari#define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ 863165138Syongari#define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ 864165138Syongari#define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ 865165138Syongari#define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ 866165138Syongari#define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ 867165138Syongari#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ 868165138Syongari#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ 869165138Syongari#define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ 870165138Syongari#define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ 871165138Syongari#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ 872165138Syongari#define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ 873165138Syongari#define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ 874165138Syongari#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ 875165138Syongari#define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ 876165138Syongari#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ 877165138Syongari#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ 878165138Syongari#define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ 879165138Syongari 880165138Syongari#define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ 881165138Syongari Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) 882165138Syongari#define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ 883165138Syongari Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) 884165138Syongari 885165138Syongari#define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ 886165138Syongari Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ 887165138Syongari Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) 888165138Syongari 889165138Syongari/* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 890165138Syongari#define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ 891165138Syongari#define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ 892165138Syongari#define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ 893165138Syongari 894165138Syongari/* B2_CHIP_ID 8 bit Chip Identification Number */ 895165138Syongari#define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ 896165138Syongari#define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ 897165138Syongari#define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 898165138Syongari#define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ 899165138Syongari#define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ 900165138Syongari#define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ 901193293Syongari#define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ 902165138Syongari#define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ 903165138Syongari#define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ 904192734Syongari#define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ 905199012Syongari#define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ 906199012Syongari#define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ 907207445Syongari#define CHIP_ID_YUKON_UNKNOWN 0xbb 908207445Syongari#define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */ 909165138Syongari 910165138Syongari#define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ 911165138Syongari#define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ 912165138Syongari#define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ 913165138Syongari#define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ 914165138Syongari 915165138Syongari#define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ 916165138Syongari#define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ 917165138Syongari#define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ 918165138Syongari 919173769Syongari#define CHIP_REV_YU_EC_U_A0 1 920173769Syongari#define CHIP_REV_YU_EC_U_A1 2 921165138Syongari 922192734Syongari#define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ 923192734Syongari 924193293Syongari#define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ 925193293Syongari#define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ 926193293Syongari 927222230Syongari#define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */ 928222230Syongari#define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */ 929222230Syongari#define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */ 930222230Syongari 931165138Syongari/* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 932165138Syongari#define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ 933165138Syongari#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ 934165138Syongari#define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ 935165138Syongari#define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ 936165138Syongari#define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ 937165138Syongari#define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ 938165138Syongari#define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ 939165138Syongari#define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ 940165138Syongari 941165138Syongari/* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 942165138Syongari#define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ 943165138Syongari#define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ 944165138Syongari#define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ 945165138Syongari 946165138Syongari#define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 947165138Syongari#define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 948165138Syongari 949165138Syongari/* B2_E_3 8 bit lower 4 bits used for HW self test result */ 950165138Syongari#define B2_E3_RES_MASK 0x0f 951165138Syongari 952165138Syongari/* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ 953165138Syongari/* Yukon-EC/FE */ 954165138Syongari#define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ 955165138Syongari#define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) 956165138Syongari/* Yukon-2 */ 957165138Syongari#define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ 958165138Syongari#define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ 959165138Syongari#define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) 960165138Syongari#define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) 961165138Syongari#define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ 962165138Syongari#define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ 963165138Syongari 964165138Syongari/* B2_TI_CTRL 8 bit Timer control */ 965165138Syongari/* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 966165138Syongari#define TIM_START BIT_2 /* Start Timer */ 967165138Syongari#define TIM_STOP BIT_1 /* Stop Timer */ 968165138Syongari#define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ 969165138Syongari 970165138Syongari/* B2_TI_TEST 8 Bit Timer Test */ 971165138Syongari/* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 972165138Syongari/* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 973165138Syongari#define TIM_T_ON BIT_2 /* Test mode on */ 974165138Syongari#define TIM_T_OFF BIT_1 /* Test mode off */ 975165138Syongari#define TIM_T_STEP BIT_0 /* Test step */ 976165138Syongari 977165138Syongari/* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ 978165138Syongari/* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ 979165138Syongari#define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ 980165138Syongari 981165138Syongari/* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 982165138Syongari#define DPT_START BIT_1 /* Start Descriptor Poll Timer */ 983165138Syongari#define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ 984165138Syongari 985165138Syongari/* B2_TST_CTRL1 8 bit Test Control Register 1 */ 986165138Syongari#define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ 987165138Syongari#define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ 988165138Syongari#define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ 989165138Syongari#define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ 990165138Syongari#define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ 991165138Syongari#define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ 992165138Syongari#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ 993165138Syongari#define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ 994165138Syongari 995193293Syongari/* B2_GP_IO */ 996193293Syongari#define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ 997193293Syongari#define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ 998193293Syongari 999193293Syongari#define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ 1000193293Syongari#define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ 1001193293Syongari#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ 1002193293Syongari#define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ 1003193293Syongari#define GLB_GPIO_TEST_SEL_BASE BIT_11 1004193293Syongari#define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ 1005193293Syongari#define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ 1006193293Syongari 1007165138Syongari/* B2_I2C_CTRL 32 bit I2C HW Control Register */ 1008165138Syongari#define I2C_FLAG BIT_31 /* Start read/write if WR */ 1009165138Syongari#define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ 1010165138Syongari#define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ 1011165138Syongari#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ 1012165138Syongari#define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ 1013165138Syongari#define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ 1014165138Syongari#define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ 1015165138Syongari#define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ 1016165138Syongari#define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ 1017165138Syongari#define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ 1018165138Syongari#define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ 1019165138Syongari#define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ 1020165138Syongari#define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ 1021165138Syongari#define I2C_STOP BIT_0 /* Interrupt I2C transfer */ 1022165138Syongari 1023165138Syongari/* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ 1024165138Syongari#define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ 1025165138Syongari 1026165138Syongari/* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ 1027165138Syongari#define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ 1028165138Syongari#define I2C_DATA BIT_1 /* I2C Data Port */ 1029165138Syongari#define I2C_CLK BIT_0 /* I2C Clock Port */ 1030165138Syongari 1031165138Syongari/* I2C Address */ 1032165138Syongari#define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ 1033165138Syongari 1034165138Syongari 1035165138Syongari/* B2_BSC_CTRL 8 bit Blink Source Counter Control */ 1036165138Syongari#define BSC_START BIT_1 /* Start Blink Source Counter */ 1037165138Syongari#define BSC_STOP BIT_0 /* Stop Blink Source Counter */ 1038165138Syongari 1039165138Syongari/* B2_BSC_STAT 8 bit Blink Source Counter Status */ 1040165138Syongari#define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ 1041165138Syongari 1042165138Syongari/* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ 1043165138Syongari#define BSC_T_ON BIT_2 /* Test mode on */ 1044165138Syongari#define BSC_T_OFF BIT_1 /* Test mode off */ 1045165138Syongari#define BSC_T_STEP BIT_0 /* Test step */ 1046165138Syongari 1047165138Syongari/* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 1048165138Syongari#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ 1049165138Syongari#define PEX_DB_ACCESS BIT_30 /* Access to debug register */ 1050165138Syongari 1051165138Syongari/* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 1052165138Syongari#define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ 1053165138Syongari 1054165138Syongari/* RAM Interface Registers */ 1055165138Syongari/* B3_RI_CTRL 16 bit RAM Interface Control Register */ 1056165138Syongari#define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ 1057165138Syongari#define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ 1058165138Syongari#define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ 1059165138Syongari#define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ 1060165138Syongari 1061165138Syongari#define MSK_RI_TO_53 36 /* RAM interface timeout */ 1062165138Syongari 1063165138Syongari/* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 1064165138Syongari/* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 1065165138Syongari/* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 1066165138Syongari/* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 1067165138Syongari/* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 1068165138Syongari#define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ 1069165138Syongari 1070165138Syongari/* TXA_CTRL 8 bit Tx Arbiter Control Register */ 1071165138Syongari#define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ 1072165138Syongari#define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ 1073165138Syongari#define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ 1074165138Syongari#define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ 1075165138Syongari#define TXA_START_RC BIT_3 /* Start sync Rate Control */ 1076165138Syongari#define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ 1077165138Syongari#define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ 1078165138Syongari#define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ 1079165138Syongari 1080165138Syongari/* TXA_TEST 8 bit Tx Arbiter Test Register */ 1081165138Syongari#define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ 1082165138Syongari#define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ 1083165138Syongari#define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ 1084165138Syongari#define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ 1085165138Syongari#define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ 1086165138Syongari#define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ 1087165138Syongari 1088165138Syongari/* TXA_STAT 8 bit Tx Arbiter Status Register */ 1089165138Syongari#define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ 1090165138Syongari 1091165138Syongari/* Q_BC 32 bit Current Byte Counter */ 1092165138Syongari#define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ 1093165138Syongari 1094165138Syongari/* Rx BMU Control / Status Registers (Yukon-2) */ 1095165138Syongari#define BMU_IDLE BIT_31 /* BMU Idle State */ 1096165138Syongari#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ 1097165138Syongari#define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ 1098165138Syongari#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ 1099165138Syongari#define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ 1100165138Syongari#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ 1101165138Syongari#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ 1102165138Syongari#define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ 1103165138Syongari#define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ 1104165138Syongari#define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ 1105165138Syongari#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ 1106165138Syongari#define BMU_START BIT_8 /* Start Rx/Tx Queue */ 1107165138Syongari#define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ 1108165138Syongari#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ 1109165138Syongari#define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ 1110165138Syongari#define BMU_FIFO_RST BIT_4 /* Reset FIFO */ 1111165138Syongari#define BMU_OP_ON BIT_3 /* BMU Operational On */ 1112165138Syongari#define BMU_OP_OFF BIT_2 /* BMU Operational Off */ 1113165138Syongari#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ 1114165138Syongari#define BMU_RST_SET BIT_0 /* Set BMU Reset */ 1115165138Syongari 1116165138Syongari#define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) 1117165138Syongari#define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \ 1118165138Syongari BMU_START | BMU_FIFO_ENA | BMU_OP_ON) 1119165138Syongari 1120165138Syongari/* Tx BMU Control / Status Registers (Yukon-2) */ 1121165138Syongari /* Bit 31: same as for Rx */ 1122165138Syongari#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ 1123165138Syongari#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ 1124165138Syongari#define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ 1125165138Syongari /* Bit 10..0: same as for Rx */ 1126165138Syongari 1127165138Syongari/* Q_F 32 bit Flag Register */ 1128193293Syongari#define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ 1129193293Syongari#define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ 1130193293Syongari#define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ 1131193293Syongari#define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ 1132193293Syongari#define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ 1133193293Syongari#define F_WM_REACHED BIT_25 /* Watermark reached */ 1134193293Syongari#define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ 1135193293Syongari#define F_FIFO_LEVEL (0x1f<<16) 1136193293Syongari /* Bit 23..16: # of Qwords in FIFO */ 1137193293Syongari#define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ 1138165138Syongari 1139165138Syongari/* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ 1140165138Syongari/* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ 1141165138Syongari#define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ 1142165138Syongari#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ 1143165138Syongari#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ 1144165138Syongari#define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ 1145165138Syongari 1146165138Syongari/* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 1147165138Syongari/* RB_START 32 bit RAM Buffer Start Address */ 1148165138Syongari/* RB_END 32 bit RAM Buffer End Address */ 1149165138Syongari/* RB_WP 32 bit RAM Buffer Write Pointer */ 1150165138Syongari/* RB_RP 32 bit RAM Buffer Read Pointer */ 1151165138Syongari/* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 1152165138Syongari/* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 1153165138Syongari/* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 1154165138Syongari/* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 1155165138Syongari/* RB_PC 32 bit RAM Buffer Packet Counter */ 1156165138Syongari/* RB_LEV 32 bit RAM Buffer Level Register */ 1157165138Syongari#define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 1158165138Syongari 1159165138Syongari/* RB_TST2 8 bit RAM Buffer Test Register 2 */ 1160165138Syongari#define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ 1161165138Syongari#define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ 1162165138Syongari#define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ 1163165138Syongari#define RB_PC_INC BIT_0 /* Packet Counter Increment */ 1164165138Syongari 1165165138Syongari/* RB_TST1 8 bit RAM Buffer Test Register 1 */ 1166165138Syongari#define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ 1167165138Syongari#define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ 1168165138Syongari#define RB_WP_INC BIT_4 /* Write Pointer Increment */ 1169165138Syongari#define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ 1170165138Syongari#define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ 1171165138Syongari#define RB_RP_INC BIT_0 /* Read Pointer Increment */ 1172165138Syongari 1173165138Syongari/* RB_CTRL 8 bit RAM Buffer Control Register */ 1174165138Syongari#define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ 1175165138Syongari#define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ 1176165138Syongari#define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ 1177165138Syongari#define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ 1178165138Syongari#define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ 1179165138Syongari#define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ 1180165138Syongari 1181165138Syongari/* RAM Buffer High Pause Threshold values */ 1182165138Syongari#define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ 1183165138Syongari#define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ 1184165138Syongari#define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ 1185165138Syongari 1186165138Syongari/* Threshold values for Yukon-EC Ultra */ 1187165138Syongari#define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ 1188165138Syongari#define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ 1189173769Syongari#define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ 1190165138Syongari#define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ 1191173769Syongari#define MSK_ECU_JUMBO_WM 0x01 1192165138Syongari 1193165138Syongari#define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ 1194165138Syongari#define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ 1195165138Syongari/* performance sensitive drivers should set this define to 0x80 */ 1196165138Syongari#define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ 1197165138Syongari 1198165138Syongari/* Receive and Transmit Queues */ 1199165138Syongari#define Q_R1 0x0000 /* Receive Queue 1 */ 1200165138Syongari#define Q_R2 0x0080 /* Receive Queue 2 */ 1201165138Syongari#define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ 1202165138Syongari#define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ 1203165138Syongari#define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ 1204165138Syongari#define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ 1205165138Syongari 1206165138Syongari#define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ 1207165138Syongari#define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ 1208165138Syongari#define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ 1209165138Syongari#define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ 1210165138Syongari 1211165138Syongari#define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) 1212165138Syongari 1213165138Syongari/* Minimum RAM Buffer Rx Queue Size */ 1214165138Syongari#define MSK_MIN_RXQ_SIZE 10 1215165138Syongari/* Minimum RAM Buffer Tx Queue Size */ 1216165138Syongari#define MSK_MIN_TXQ_SIZE 10 1217165138Syongari/* Percentage of queue size from whole memory. 80 % for receive */ 1218165138Syongari#define MSK_RAM_QUOTA_RX 80 1219165138Syongari 1220165138Syongari/* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1221165138Syongari#define WOL_CTL_LINK_CHG_OCC BIT_15 1222165138Syongari#define WOL_CTL_MAGIC_PKT_OCC BIT_14 1223165138Syongari#define WOL_CTL_PATTERN_OCC BIT_13 1224165138Syongari#define WOL_CTL_CLEAR_RESULT BIT_12 1225165138Syongari#define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 1226165138Syongari#define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 1227165138Syongari#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 1228165138Syongari#define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 1229165138Syongari#define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 1230165138Syongari#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 1231165138Syongari#define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 1232165138Syongari#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 1233165138Syongari#define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 1234165138Syongari#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 1235165138Syongari#define WOL_CTL_ENA_PATTERN_UNIT BIT_1 1236165138Syongari#define WOL_CTL_DIS_PATTERN_UNIT BIT_0 1237165138Syongari 1238165138Syongari#define WOL_CTL_DEFAULT \ 1239165138Syongari (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1240165138Syongari WOL_CTL_DIS_PME_ON_PATTERN | \ 1241165138Syongari WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1242165138Syongari WOL_CTL_DIS_LINK_CHG_UNIT | \ 1243165138Syongari WOL_CTL_DIS_PATTERN_UNIT | \ 1244165138Syongari WOL_CTL_DIS_MAGIC_PKT_UNIT) 1245165138Syongari 1246165138Syongari/* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 1247165138Syongari#define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) 1248165138Syongari 1249165138Syongari/* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ 1250165138Syongari#define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ 1251165138Syongari#define WOL_PATT_MATCH_PME_ALL 0x7f 1252165138Syongari 1253165138Syongari 1254165138Syongari/* 1255165138Syongari * Marvel-PHY Registers, indirect addressed over GMAC 1256165138Syongari */ 1257165138Syongari#define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 1258165138Syongari#define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 1259165138Syongari#define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 1260165138Syongari#define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 1261165138Syongari#define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 1262165138Syongari#define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 1263165138Syongari#define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 1264165138Syongari#define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 1265165138Syongari#define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 1266165138Syongari /* Marvel-specific registers */ 1267165138Syongari#define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 1268165138Syongari#define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 1269165138Syongari /* 0x0b - 0x0e: reserved */ 1270165138Syongari#define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 1271165138Syongari#define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ 1272165138Syongari#define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ 1273165138Syongari#define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 1274165138Syongari#define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 1275165138Syongari#define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 1276165138Syongari#define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 1277165138Syongari#define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 1278165138Syongari#define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ 1279165138Syongari#define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 1280165138Syongari#define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 1281165138Syongari#define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 1282165138Syongari#define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 1283165138Syongari#define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 1284165138Syongari#define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ 1285165138Syongari#define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ 1286165138Syongari 1287165138Syongari/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1288165138Syongari#define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ 1289165138Syongari#define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ 1290165138Syongari#define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ 1291165138Syongari#define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ 1292165138Syongari#define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ 1293165138Syongari 1294165138Syongari#define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 1295165138Syongari#define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 1296165138Syongari#define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ 1297165138Syongari#define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 1298165138Syongari#define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ 1299165138Syongari#define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ 1300165138Syongari#define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 1301165138Syongari#define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 1302165138Syongari#define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ 1303165138Syongari#define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ 1304165138Syongari 1305165138Syongari#define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 1306165138Syongari#define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 1307165138Syongari#define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 1308165138Syongari 1309165138Syongari#define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 1310165138Syongari#define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ 1311165138Syongari#define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 1312298955Spfg#define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occurred */ 1313165138Syongari#define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 1314165138Syongari#define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 1315165138Syongari#define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ 1316165138Syongari#define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 1317165138Syongari 1318165138Syongari#define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 1319165138Syongari#define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 1320165138Syongari#define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ 1321165138Syongari 1322165138Syongari/* different Marvell PHY Ids */ 1323165138Syongari#define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ 1324165138Syongari 1325165138Syongari#define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ 1326165138Syongari#define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ 1327165138Syongari#define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ 1328165138Syongari#define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ 1329165138Syongari#define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ 1330165138Syongari#define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ 1331165138Syongari 1332165138Syongari/***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1333165138Syongari#define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1334165138Syongari#define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1335165138Syongari#define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1336165138Syongari#define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 1337165138Syongari#define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1338165138Syongari#define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1339165138Syongari#define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 1340165138Syongari 1341165138Syongari/***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 1342165138Syongari/***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 1343165138Syongari#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 1344165138Syongari#define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 1345165138Syongari#define PHY_M_AN_RF BIT_13 /* Remote Fault */ 1346165138Syongari#define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 1347165138Syongari#define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 1348165138Syongari#define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ 1349165138Syongari#define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 1350165138Syongari#define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 1351165138Syongari#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 1352165138Syongari#define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 1353165138Syongari#define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ 1354165138Syongari 1355165138Syongari/* special defines for FIBER (88E1011S only) */ 1356165138Syongari#define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 1357165138Syongari#define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 1358165138Syongari#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 1359165138Syongari#define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 1360165138Syongari 1361165138Syongari/* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1362165138Syongari#define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 1363165138Syongari#define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 1364165138Syongari#define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 1365165138Syongari#define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 1366165138Syongari 1367165138Syongari/***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1368165138Syongari#define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1369165138Syongari#define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ 1370165138Syongari#define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ 1371165138Syongari#define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ 1372165138Syongari#define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ 1373165138Syongari#define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ 1374165138Syongari 1375165138Syongari/***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1376165138Syongari#define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 1377165138Syongari#define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 1378165138Syongari#define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ 1379165138Syongari#define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ 1380165138Syongari#define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 1381165138Syongari#define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ 1382165138Syongari#define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 1383165138Syongari#define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ 1384165138Syongari#define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ 1385165138Syongari#define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ 1386165138Syongari#define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ 1387165138Syongari#define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ 1388165138Syongari 1389165138Syongari#define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 1390165138Syongari#define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 1391165138Syongari 1392165138Syongari#define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) 1393165138Syongari 1394165138Syongari#define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 1395165138Syongari#define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 1396165138Syongari#define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 1397165138Syongari 1398165138Syongari/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1399165138Syongari#define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ 1400165138Syongari#define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ 1401165138Syongari#define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ 1402165138Syongari /* !!! Errata in spec. (1 = disable) */ 1403165138Syongari 1404165138Syongari#define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) 1405165138Syongari /* 000=1x; 001=2x; 010=3x; 011=4x */ 1406165138Syongari /* 100=5x; 101=6x; 110=7x; 111=8x */ 1407165138Syongari 1408165138Syongari/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1409165138Syongari#define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ 1410165138Syongari#define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ 1411165138Syongari#define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ 1412165138Syongari#define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ 1413165138Syongari#define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ 1414165138Syongari#define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ 1415165138Syongari#define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ 1416165138Syongari#define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ 1417165138Syongari#define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ 1418165138Syongari 1419165138Syongari/***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1420165138Syongari#define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 1421165138Syongari#define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ 1422165138Syongari#define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ 1423165138Syongari#define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 1424165138Syongari#define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ 1425165138Syongari#define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ 1426165138Syongari#define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ 1427165138Syongari#define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ 1428165138Syongari#define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ 1429165138Syongari#define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ 1430165138Syongari#define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ 1431165138Syongari#define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ 1432165138Syongari#define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ 1433165138Syongari#define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ 1434165138Syongari#define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ 1435165138Syongari#define PHY_M_PS_JABBER BIT_0 /* Jabber */ 1436165138Syongari 1437165138Syongari#define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1438165138Syongari 1439165138Syongari/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1440165138Syongari#define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ 1441165138Syongari#define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1442165138Syongari 1443165138Syongari/***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 1444165138Syongari/***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 1445165138Syongari#define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ 1446165138Syongari#define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ 1447165138Syongari#define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ 1448165138Syongari#define PHY_M_IS_AN_PR BIT_12 /* Page Received */ 1449165138Syongari#define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ 1450165138Syongari#define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ 1451165138Syongari#define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ 1452165138Syongari#define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ 1453165138Syongari#define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ 1454165138Syongari#define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ 1455165138Syongari#define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ 1456165138Syongari#define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ 1457165138Syongari#define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ 1458165138Syongari#define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ 1459165138Syongari#define PHY_M_IS_JABBER BIT_0 /* Jabber */ 1460165138Syongari 1461165138Syongari#define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 1462165138Syongari PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 1463165138Syongari 1464165138Syongari/***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1465165138Syongari#define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ 1466165138Syongari#define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ 1467165138Syongari#define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ 1468165138Syongari#define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ 1469165138Syongari /* (88E1011 only) */ 1470165138Syongari#define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ 1471165138Syongari /* (88E1011 only) */ 1472165138Syongari#define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ 1473165138Syongari /* (88E1111 only) */ 1474165138Syongari#define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ 1475165138Syongari /* !!! Errata in spec. (1 = disable) */ 1476165138Syongari#define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ 1477165138Syongari#define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 1478165138Syongari#define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ 1479165138Syongari#define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ 1480165138Syongari#define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ 1481165138Syongari#define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ 1482165138Syongari 1483165138Syongari#define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) 1484165138Syongari /* 00=1x; 01=2x; 10=3x; 11=4x */ 1485165138Syongari#define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) 1486165138Syongari /* 00=dis; 01=1x; 10=2x; 11=3x */ 1487165138Syongari#define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) 1488165138Syongari /* 01X=0; 110=2.5; 111=25 (MHz) */ 1489165138Syongari 1490165138Syongari#define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) 1491165138Syongari /* 000=1x; 001=2x; 010=3x; 011=4x */ 1492165138Syongari /* 100=5x; 101=6x; 110=7x; 111=8x */ 1493165138Syongari#define MAC_TX_CLK_0_MHZ 2 1494165138Syongari#define MAC_TX_CLK_2_5_MHZ 6 1495165138Syongari#define MAC_TX_CLK_25_MHZ 7 1496165138Syongari 1497165138Syongari/***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1498165138Syongari#define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ 1499165138Syongari#define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 1500165138Syongari#define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ 1501165138Syongari#define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 1502165138Syongari#define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ 1503165138Syongari#define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ 1504165138Syongari#define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ 1505165138Syongari /* (88E1111 only) */ 1506165138Syongari#define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 1507165138Syongari /* (88E1011 only) */ 1508165138Syongari#define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ 1509165138Syongari#define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ 1510165138Syongari#define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ 1511165138Syongari#define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ 1512165138Syongari#define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ 1513165138Syongari 1514165138Syongari#define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) 1515165138Syongari 1516165138Syongari#define PULS_NO_STR 0 /* no pulse stretching */ 1517165138Syongari#define PULS_21MS 1 /* 21 ms to 42 ms */ 1518165138Syongari#define PULS_42MS 2 /* 42 ms to 84 ms */ 1519165138Syongari#define PULS_84MS 3 /* 84 ms to 170 ms */ 1520165138Syongari#define PULS_170MS 4 /* 170 ms to 340 ms */ 1521165138Syongari#define PULS_340MS 5 /* 340 ms to 670 ms */ 1522165138Syongari#define PULS_670MS 6 /* 670 ms to 1.3 s */ 1523165138Syongari#define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 1524165138Syongari 1525165138Syongari#define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) 1526165138Syongari 1527165138Syongari#define BLINK_42MS 0 /* 42 ms */ 1528165138Syongari#define BLINK_84MS 1 /* 84 ms */ 1529165138Syongari#define BLINK_170MS 2 /* 170 ms */ 1530165138Syongari#define BLINK_340MS 3 /* 340 ms */ 1531165138Syongari#define BLINK_670MS 4 /* 670 ms */ 1532165138Syongari 1533165138Syongari/***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1534165138Syongari#define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ 1535165138Syongari#define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 1536165138Syongari#define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 1537165138Syongari#define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 1538165138Syongari#define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 1539165138Syongari#define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 1540165138Syongari#define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 1541165138Syongari 1542165138Syongari#define MO_LED_NORM 0 1543165138Syongari#define MO_LED_BLINK 1 1544165138Syongari#define MO_LED_OFF 2 1545165138Syongari#define MO_LED_ON 3 1546165138Syongari 1547165138Syongari/***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1548165138Syongari#define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ 1549165138Syongari#define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ 1550165138Syongari#define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ 1551165138Syongari#define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ 1552165138Syongari#define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 1553165138Syongari 1554165138Syongari/***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1555165138Syongari#define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ 1556165138Syongari#define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ 1557165138Syongari#define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ 1558165138Syongari#define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ 1559165138Syongari#define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ 1560165138Syongari#define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ 1561165138Syongari#define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ 1562165138Syongari /* (88E1111 only) */ 1563165138Syongari#define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ 1564165138Syongari#define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ 1565165138Syongari#define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1566165138Syongari 1567165138Syongari/***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 1568165138Syongari#define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ 1569165138Syongari#define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ 1570165138Syongari /* (88E1111 only) */ 1571165138Syongari#define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ 1572165138Syongari#define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ 1573165138Syongari /* (88E1111 only) */ 1574165138Syongari#define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ 1575165138Syongari 1576165138Syongari/* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 1577165138Syongari#define CABD_STAT_NORMAL 0 1578165138Syongari#define CABD_STAT_SHORT 1 1579165138Syongari#define CABD_STAT_OPEN 2 1580165138Syongari#define CABD_STAT_FAIL 3 1581165138Syongari 1582165138Syongari/* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1583165138Syongari/***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1584165138Syongari#define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ 1585165138Syongari#define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ 1586165138Syongari#define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ 1587165138Syongari 1588165138Syongari#define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) 1589165138Syongari#define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) 1590165138Syongari#define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) 1591165138Syongari 1592165138Syongari#define LED_PAR_CTRL_COLX 0x00 1593165138Syongari#define LED_PAR_CTRL_ERROR 0x01 1594165138Syongari#define LED_PAR_CTRL_DUPLEX 0x02 1595165138Syongari#define LED_PAR_CTRL_DP_COL 0x03 1596165138Syongari#define LED_PAR_CTRL_SPEED 0x04 1597165138Syongari#define LED_PAR_CTRL_LINK 0x05 1598165138Syongari#define LED_PAR_CTRL_TX 0x06 1599165138Syongari#define LED_PAR_CTRL_RX 0x07 1600165138Syongari#define LED_PAR_CTRL_ACT 0x08 1601165138Syongari#define LED_PAR_CTRL_LNK_RX 0x09 1602165138Syongari#define LED_PAR_CTRL_LNK_AC 0x0a 1603165138Syongari#define LED_PAR_CTRL_ACT_BL 0x0b 1604165138Syongari#define LED_PAR_CTRL_TX_BL 0x0c 1605165138Syongari#define LED_PAR_CTRL_RX_BL 0x0d 1606165138Syongari#define LED_PAR_CTRL_COL_BL 0x0e 1607165138Syongari#define LED_PAR_CTRL_INACT 0x0f 1608165138Syongari 1609165138Syongari/***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1610165138Syongari#define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ 1611165138Syongari#define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ 1612165138Syongari#define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ 1613165138Syongari 1614165138Syongari/* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1615165138Syongari/***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1616165138Syongari#define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ 1617165138Syongari#define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ 1618165138Syongari#define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ 1619165138Syongari 1620165138Syongari/***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1621165138Syongari#define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ 1622165138Syongari#define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ 1623165138Syongari#define PHY_M_MAC_MD_COPPER 5 /* Copper only */ 1624165138Syongari#define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ 1625165138Syongari#define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) 1626165138Syongari 1627165138Syongari/***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1628165138Syongari#define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ 1629165138Syongari#define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1630165138Syongari#define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1631165138Syongari#define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1632165138Syongari 1633165138Syongari#define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) 1634165138Syongari#define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) 1635165138Syongari#define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) 1636165138Syongari#define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) 1637165138Syongari 1638165138Syongari/***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ 1639165138Syongari#define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1640165138Syongari#define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1641165138Syongari#define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1642165138Syongari#define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1643165138Syongari#define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1644165138Syongari#define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1645165138Syongari 1646165138Syongari#define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) 1647165138Syongari#define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) 1648165138Syongari#define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) 1649165138Syongari#define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) 1650165138Syongari#define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) 1651165138Syongari#define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) 1652165138Syongari 1653165138Syongari/* 1654165138Syongari * GMAC registers 1655165138Syongari * 1656165138Syongari * The GMAC registers are 16 or 32 bits wide. 1657165138Syongari * The GMACs host processor interface is 16 bits wide, 1658165138Syongari * therefore ALL registers will be addressed with 16 bit accesses. 1659165138Syongari * 1660165138Syongari * Note: NA reg = Network Address e.g DA, SA etc. 1661165138Syongari */ 1662165138Syongari 1663165138Syongari/* Port Registers */ 1664165138Syongari#define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 1665165138Syongari#define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 1666165138Syongari#define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 1667165138Syongari#define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 1668165138Syongari#define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 1669165138Syongari#define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 1670165138Syongari#define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 1671165138Syongari 1672165138Syongari/* Source Address Registers */ 1673165138Syongari#define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 1674165138Syongari#define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 1675165138Syongari#define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 1676165138Syongari#define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 1677165138Syongari#define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 1678165138Syongari#define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 1679165138Syongari 1680165138Syongari/* Multicast Address Hash Registers */ 1681165138Syongari#define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 1682165138Syongari#define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 1683165138Syongari#define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 1684165138Syongari#define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 1685165138Syongari 1686165138Syongari/* Interrupt Source Registers */ 1687165138Syongari#define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 1688165138Syongari#define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 1689165138Syongari#define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1690165138Syongari 1691165138Syongari/* Interrupt Mask Registers */ 1692165138Syongari#define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 1693165138Syongari#define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 1694165138Syongari#define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1695165138Syongari 1696165138Syongari/* Serial Management Interface (SMI) Registers */ 1697165138Syongari#define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 1698165138Syongari#define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 1699165138Syongari#define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 1700165138Syongari 1701165138Syongari/* MIB Counters */ 1702165138Syongari#define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1703165138Syongari#define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1704165138Syongari 1705165138Syongari/* 1706165138Syongari * MIB Counters base address definitions (low word) - 1707165138Syongari * use offset 4 for access to high word (32 bit r/o) 1708165138Syongari */ 1709165138Syongari#define GM_RXF_UC_OK \ 1710165138Syongari (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 1711165138Syongari#define GM_RXF_BC_OK \ 1712165138Syongari (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 1713165138Syongari#define GM_RXF_MPAUSE \ 1714165138Syongari (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 1715165138Syongari#define GM_RXF_MC_OK \ 1716165138Syongari (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 1717165138Syongari#define GM_RXF_FCS_ERR \ 1718165138Syongari (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 1719187325Syongari#define GM_RXF_SPARE1 \ 1720187325Syongari (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ 1721165138Syongari#define GM_RXO_OK_LO \ 1722165138Syongari (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 1723165138Syongari#define GM_RXO_OK_HI \ 1724165138Syongari (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 1725165138Syongari#define GM_RXO_ERR_LO \ 1726165138Syongari (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 1727165138Syongari#define GM_RXO_ERR_HI \ 1728165138Syongari (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 1729165138Syongari#define GM_RXF_SHT \ 1730165138Syongari (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 1731165138Syongari#define GM_RXE_FRAG \ 1732165138Syongari (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 1733165138Syongari#define GM_RXF_64B \ 1734165138Syongari (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 1735165138Syongari#define GM_RXF_127B \ 1736165138Syongari (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 1737165138Syongari#define GM_RXF_255B \ 1738165138Syongari (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 1739165138Syongari#define GM_RXF_511B \ 1740165138Syongari (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 1741165138Syongari#define GM_RXF_1023B \ 1742165138Syongari (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 1743165138Syongari#define GM_RXF_1518B \ 1744165138Syongari (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 1745165138Syongari#define GM_RXF_MAX_SZ \ 1746165138Syongari (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 1747165138Syongari#define GM_RXF_LNG_ERR \ 1748165138Syongari (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 1749165138Syongari#define GM_RXF_JAB_PKT \ 1750165138Syongari (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 1751187325Syongari#define GM_RXF_SPARE2 \ 1752187325Syongari (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ 1753165138Syongari#define GM_RXE_FIFO_OV \ 1754165138Syongari (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 1755187325Syongari#define GM_RXF_SPARE3 \ 1756187325Syongari (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ 1757165138Syongari#define GM_TXF_UC_OK \ 1758165138Syongari (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 1759165138Syongari#define GM_TXF_BC_OK \ 1760165138Syongari (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 1761165138Syongari#define GM_TXF_MPAUSE \ 1762165138Syongari (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 1763165138Syongari#define GM_TXF_MC_OK \ 1764165138Syongari (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 1765165138Syongari#define GM_TXO_OK_LO \ 1766165138Syongari (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 1767165138Syongari#define GM_TXO_OK_HI \ 1768165138Syongari (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 1769165138Syongari#define GM_TXF_64B \ 1770165138Syongari (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 1771165138Syongari#define GM_TXF_127B \ 1772165138Syongari (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 1773165138Syongari#define GM_TXF_255B \ 1774165138Syongari (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 1775165138Syongari#define GM_TXF_511B \ 1776165138Syongari (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 1777165138Syongari#define GM_TXF_1023B \ 1778165138Syongari (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 1779165138Syongari#define GM_TXF_1518B \ 1780165138Syongari (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 1781165138Syongari#define GM_TXF_MAX_SZ \ 1782165138Syongari (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 1783187325Syongari#define GM_TXF_SPARE1 \ 1784187325Syongari (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ 1785165138Syongari#define GM_TXF_COL \ 1786165138Syongari (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 1787165138Syongari#define GM_TXF_LAT_COL \ 1788165138Syongari (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 1789165138Syongari#define GM_TXF_ABO_COL \ 1790165138Syongari (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 1791165138Syongari#define GM_TXF_MUL_COL \ 1792165138Syongari (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 1793165138Syongari#define GM_TXF_SNG_COL \ 1794165138Syongari (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 1795165138Syongari#define GM_TXE_FIFO_UR \ 1796165138Syongari (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 1797165138Syongari 1798165138Syongari/*----------------------------------------------------------------------------*/ 1799165138Syongari/* 1800165138Syongari * GMAC Bit Definitions 1801165138Syongari * 1802165138Syongari * If the bit access behaviour differs from the register access behaviour 1803165138Syongari * (r/w, r/o) this is documented after the bit number. 1804165138Syongari * The following bit access behaviours are used: 1805165138Syongari * (sc) self clearing 1806165138Syongari * (r/o) read only 1807165138Syongari */ 1808165138Syongari 1809165138Syongari/* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1810165138Syongari#define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ 1811165138Syongari#define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ 1812165138Syongari#define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ 1813165138Syongari#define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ 1814165138Syongari#define GM_GPSR_PAUSE BIT_11 /* Pause State */ 1815165138Syongari#define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ 1816298955Spfg#define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occurred */ 1817298955Spfg#define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occurred */ 1818165138Syongari#define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ 1819165138Syongari#define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ 1820165138Syongari#define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ 1821165138Syongari#define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ 1822165138Syongari 1823165138Syongari/* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1824165138Syongari#define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ 1825165138Syongari#define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ 1826165138Syongari#define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ 1827165138Syongari#define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ 1828165138Syongari#define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ 1829165138Syongari#define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ 1830165138Syongari#define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ 1831165138Syongari#define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ 1832165138Syongari#define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ 1833165138Syongari#define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ 1834165138Syongari#define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ 1835165138Syongari#define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ 1836165138Syongari#define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ 1837165138Syongari#define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ 1838165138Syongari#define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ 1839165138Syongari 1840165138Syongari#define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1841165138Syongari#define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 1842165138Syongari GM_GPCR_AU_SPD_DIS) 1843165138Syongari 1844165138Syongari/* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1845165138Syongari#define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ 1846165138Syongari#define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ 1847165138Syongari#define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ 1848165138Syongari#define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ 1849165138Syongari#define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ 1850165138Syongari /* (Yukon-2 only) */ 1851165138Syongari 1852165138Syongari#define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1853165138Syongari#define TX_COL_DEF 0x04 1854165138Syongari 1855165138Syongari/* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1856165138Syongari#define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ 1857165138Syongari#define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ 1858165138Syongari#define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ 1859165138Syongari#define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ 1860165138Syongari 1861165138Syongari/* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1862165138Syongari#define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ 1863165138Syongari#define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ 1864165138Syongari#define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ 1865165138Syongari#define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ 1866165138Syongari /* (Yukon-2 only) */ 1867165138Syongari 1868165138Syongari#define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 1869165138Syongari#define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 1870165138Syongari#define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 1871165138Syongari#define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1872165138Syongari 1873165138Syongari#define TX_JAM_LEN_DEF 0x03 1874165138Syongari#define TX_JAM_IPG_DEF 0x0b 1875165138Syongari#define TX_IPG_JAM_DEF 0x1c 1876165138Syongari#define TX_BOF_LIM_DEF 0x04 1877165138Syongari 1878165138Syongari/* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1879165138Syongari#define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ 1880165138Syongari /* r/o on Yukon, r/w on Yukon-EC */ 1881165138Syongari#define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ 1882165138Syongari#define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ 1883165138Syongari#define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ 1884165138Syongari#define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ 1885165138Syongari 1886165138Syongari#define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 1887165138Syongari#define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) 1888165138Syongari 1889165138Syongari#define DATA_BLIND_DEF 0x04 1890165138Syongari#define IPG_DATA_DEF 0x1e 1891165138Syongari 1892165138Syongari/* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1893165138Syongari#define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 1894165138Syongari#define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 1895165138Syongari#define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ 1896165138Syongari#define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ 1897165138Syongari#define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ 1898165138Syongari 1899165138Syongari#define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 1900165138Syongari#define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 1901165138Syongari 1902165138Syongari/* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1903165138Syongari#define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ 1904165138Syongari#define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ 1905165138Syongari 1906165138Syongari/* Receive Frame Status Encoding */ 1907165138Syongari#define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ 1908165138Syongari#define GMR_FS_VLAN BIT_13 /* VLAN Packet */ 1909165138Syongari#define GMR_FS_JABBER BIT_12 /* Jabber Packet */ 1910165138Syongari#define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ 1911165138Syongari#define GMR_FS_MC BIT_10 /* Multicast Packet */ 1912165138Syongari#define GMR_FS_BC BIT_9 /* Broadcast Packet */ 1913165138Syongari#define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ 1914165138Syongari#define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ 1915165138Syongari#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ 1916165138Syongari#define GMR_FS_MII_ERR BIT_5 /* MII Error */ 1917165138Syongari#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ 1918165138Syongari#define GMR_FS_FRAGMENT BIT_3 /* Fragment */ 1919165138Syongari#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ 1920165138Syongari#define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ 1921165138Syongari 1922165138Syongari#define GMR_FS_LEN_SHIFT 16 1923165138Syongari 1924165138Syongari#define GMR_FS_ANY_ERR ( \ 1925165138Syongari GMR_FS_RX_FF_OV | \ 1926165138Syongari GMR_FS_CRC_ERR | \ 1927165138Syongari GMR_FS_FRAGMENT | \ 1928165138Syongari GMR_FS_LONG_ERR | \ 1929165138Syongari GMR_FS_MII_ERR | \ 1930165138Syongari GMR_FS_BAD_FC | \ 1931176652Syongari GMR_FS_GOOD_FC | \ 1932165138Syongari GMR_FS_UN_SIZE | \ 1933165138Syongari GMR_FS_JABBER) 1934165138Syongari 1935165138Syongari/* Rx GMAC FIFO Flush Mask (default) */ 1936165138Syongari#define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR 1937165138Syongari 1938165138Syongari/* Receive and Transmit GMAC FIFO Registers (YUKON only) */ 1939165138Syongari 1940165138Syongari/* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ 1941165138Syongari/* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ 1942165138Syongari/* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ 1943165138Syongari/* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ 1944165138Syongari/* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ 1945165138Syongari/* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ 1946165138Syongari/* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 1947165138Syongari/* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 1948165138Syongari/* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ 1949165138Syongari/* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ 1950165138Syongari/* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ 1951165138Syongari/* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ 1952165138Syongari/* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ 1953165138Syongari/* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ 1954165138Syongari 1955165138Syongari/* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1956165138Syongari#define RX_TRUNC_ON BIT_27 /* enable packet truncation */ 1957165138Syongari#define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ 1958165138Syongari#define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ 1959165138Syongari#define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ 1960207442Syongari#define GMF_RX_MACSEC_FLUSH_ON BIT_23 1961207442Syongari#define GMF_RX_MACSEC_FLUSH_OFF BIT_22 1962192734Syongari#define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ 1963192734Syongari#define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ 1964192734Syongari#define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ 1965192734Syongari#define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ 1966165138Syongari#define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ 1967165138Syongari#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ 1968165138Syongari#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ 1969165138Syongari#define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ 1970165138Syongari#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ 1971165138Syongari#define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ 1972165138Syongari#define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ 1973165138Syongari#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ 1974165138Syongari#define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ 1975165138Syongari#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ 1976165138Syongari#define GMF_OPER_ON BIT_3 /* Operational Mode On */ 1977165138Syongari#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ 1978165138Syongari#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ 1979165138Syongari#define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ 1980165138Syongari 1981165138Syongari/* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ 1982165138Syongari#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ 1983165138Syongari#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ 1984165138Syongari#define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ 1985165138Syongari#define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ 1986173769Syongari#define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ 1987173769Syongari#define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ 1988165138Syongari#define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ 1989165138Syongari#define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ 1990165138Syongari#define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ 1991165138Syongari /* Bits 15..8: same as for RX_GMF_CTRL_T */ 1992165138Syongari#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ 1993165138Syongari#define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ 1994165138Syongari#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ 1995165138Syongari /* Bits 3..0: same as for RX_GMF_CTRL_T */ 1996165138Syongari 1997165138Syongari#define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) 1998165138Syongari#define GMF_TX_CTRL_DEF GMF_OPER_ON 1999165138Syongari 2000165138Syongari#define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ 2001165138Syongari#define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ 2002165138Syongari 2003165138Syongari/* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 2004165138Syongari#define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ 2005165138Syongari#define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ 2006165138Syongari#define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ 2007165138Syongari 2008165138Syongari/* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ 2009165138Syongari#define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ 2010165138Syongari#define PC_POLL_RQ BIT_4 /* Poll Request Start */ 2011165138Syongari#define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ 2012165138Syongari#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ 2013165138Syongari#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ 2014165138Syongari#define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ 2015165138Syongari 2016165138Syongari/* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 2017165138Syongari/* This register is used by the host driver software */ 2018165138Syongari#define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ 2019165138Syongari#define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ 2020165138Syongari#define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ 2021165138Syongari#define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ 2022165138Syongari#define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ 2023165138Syongari 2024165138Syongari#define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ 2025165138Syongari#define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ 2026165138Syongari 2027193293Syongari/* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */ 2028193293Syongari#define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ 2029193293Syongari#define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ 2030193293Syongari#define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ 2031193293Syongari#define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ 2032193293Syongari#define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ 2033193293Syongari#define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ 2034193293Syongari#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ 2035193293Syongari#define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ 2036193293Syongari#define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 2037193293Syongari#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 2038193293Syongari#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 2039193293Syongari#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */ 2040193293Syongari#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 2041193293Syongari#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ 2042193293Syongari /* Microcontroller State */ 2043193293Syongari#define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 2044193293Syongari#define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 2045193293Syongari#define Y2_ASF_HCU_CCSR_ASF_RESET 0 2046193293Syongari#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 2047193293Syongari#define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 2048193293Syongari 2049165138Syongari/* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 2050165138Syongari/* This register is used by the ASF firmware */ 2051165138Syongari#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ 2052165138Syongari#define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ 2053165138Syongari 2054165138Syongari/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 2055165138Syongari#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ 2056165138Syongari#define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ 2057165138Syongari#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ 2058165138Syongari#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ 2059165138Syongari#define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ 2060165138Syongari 2061165138Syongari/* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 2062193293Syongari#define GMC_SEC_RST BIT_15 /* MAC SEC RST */ 2063193293Syongari#define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ 2064193293Syongari#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ 2065193293Syongari#define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ 2066193293Syongari#define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ 2067193293Syongari#define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ 2068193293Syongari#define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ 2069193293Syongari#define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ 2070165138Syongari#define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ 2071165138Syongari#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ 2072165138Syongari#define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ 2073165138Syongari#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ 2074165138Syongari#define GMC_PAUSE_ON BIT_3 /* Pause On */ 2075165138Syongari#define GMC_PAUSE_OFF BIT_2 /* Pause Off */ 2076165138Syongari#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ 2077165138Syongari#define GMC_RST_SET BIT_0 /* Set GMAC Reset */ 2078165138Syongari 2079165138Syongari/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 2080165138Syongari#define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ 2081165138Syongari#define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ 2082165138Syongari#define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ 2083165138Syongari#define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ 2084165138Syongari#define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ 2085165138Syongari#define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ 2086165138Syongari#define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ 2087165138Syongari#define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ 2088165138Syongari#define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ 2089165138Syongari#define GPC_ANEG_0 BIT_19 /* ANEG[0] */ 2090165138Syongari#define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ 2091165138Syongari#define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ 2092165138Syongari#define GPC_ANEG_3 BIT_16 /* ANEG[3] */ 2093165138Syongari#define GPC_ANEG_2 BIT_15 /* ANEG[2] */ 2094165138Syongari#define GPC_ANEG_1 BIT_14 /* ANEG[1] */ 2095165138Syongari#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ 2096165138Syongari#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ 2097165138Syongari#define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ 2098165138Syongari#define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ 2099165138Syongari#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ 2100165138Syongari#define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ 2101165138Syongari#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ 2102165138Syongari#define GPC_RST_SET BIT_0 /* Set GPHY Reset */ 2103165138Syongari 2104165138Syongari/* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 2105165138Syongari/* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 2106165138Syongari#define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ 2107165138Syongari#define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ 2108165138Syongari#define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ 2109165138Syongari#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ 2110165138Syongari#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ 2111165138Syongari#define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ 2112165138Syongari 2113165138Syongari#define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) 2114165138Syongari 2115165138Syongari/* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 2116165138Syongari#define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ 2117165138Syongari#define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ 2118165138Syongari 2119165138Syongari#define MSK_PORT_A 0 2120165138Syongari#define MSK_PORT_B 1 2121165138Syongari 2122165138Syongari/* Register access macros */ 2123165138Syongari#define CSR_WRITE_4(sc, reg, val) \ 2124165138Syongari bus_write_4((sc)->msk_res[0], (reg), (val)) 2125165138Syongari#define CSR_WRITE_2(sc, reg, val) \ 2126165138Syongari bus_write_2((sc)->msk_res[0], (reg), (val)) 2127165138Syongari#define CSR_WRITE_1(sc, reg, val) \ 2128165138Syongari bus_write_1((sc)->msk_res[0], (reg), (val)) 2129165138Syongari 2130165138Syongari#define CSR_READ_4(sc, reg) \ 2131165138Syongari bus_read_4((sc)->msk_res[0], (reg)) 2132165138Syongari#define CSR_READ_2(sc, reg) \ 2133165138Syongari bus_read_2((sc)->msk_res[0], (reg)) 2134165138Syongari#define CSR_READ_1(sc, reg) \ 2135165138Syongari bus_read_1((sc)->msk_res[0], (reg)) 2136165138Syongari 2137165138Syongari#define CSR_PCI_WRITE_4(sc, reg, val) \ 2138165138Syongari bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2139165138Syongari#define CSR_PCI_WRITE_2(sc, reg, val) \ 2140165138Syongari bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2141165138Syongari#define CSR_PCI_WRITE_1(sc, reg, val) \ 2142165138Syongari bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2143165138Syongari 2144165138Syongari#define CSR_PCI_READ_4(sc, reg) \ 2145165138Syongari bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2146165138Syongari#define CSR_PCI_READ_2(sc, reg) \ 2147165138Syongari bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2148165138Syongari#define CSR_PCI_READ_1(sc, reg) \ 2149165138Syongari bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2150165138Syongari 2151165138Syongari#define MSK_IF_READ_4(sc_if, reg) \ 2152165138Syongari CSR_READ_4((sc_if)->msk_softc, (reg)) 2153165138Syongari#define MSK_IF_READ_2(sc_if, reg) \ 2154165138Syongari CSR_READ_2((sc_if)->msk_softc, (reg)) 2155165138Syongari#define MSK_IF_READ_1(sc_if, reg) \ 2156165138Syongari CSR_READ_1((sc_if)->msk_softc, (reg)) 2157165138Syongari 2158165138Syongari#define MSK_IF_WRITE_4(sc_if, reg, val) \ 2159165138Syongari CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) 2160165138Syongari#define MSK_IF_WRITE_2(sc_if, reg, val) \ 2161165138Syongari CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) 2162165138Syongari#define MSK_IF_WRITE_1(sc_if, reg, val) \ 2163165138Syongari CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) 2164165138Syongari 2165165138Syongari#define GMAC_REG(port, reg) \ 2166165138Syongari ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) 2167165138Syongari#define GMAC_WRITE_2(sc, port, reg, val) \ 2168165138Syongari CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) 2169165138Syongari#define GMAC_READ_2(sc, port, reg) \ 2170165138Syongari CSR_READ_2((sc), GMAC_REG((port), (reg))) 2171165138Syongari 2172165138Syongari/* GPHY address (bits 15..11 of SMI control reg) */ 2173165138Syongari#define PHY_ADDR_MARV 0 2174165138Syongari 2175165138Syongari#define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 2176165138Syongari#define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 2177165138Syongari 2178287238Syongari#define MSK_RING_ALIGN 32768 2179287238Syongari#define MSK_STAT_ALIGN 32768 2180165138Syongari 2181165138Syongari/* Rx descriptor data structure */ 2182165138Syongaristruct msk_rx_desc { 2183165138Syongari uint32_t msk_addr; 2184165138Syongari uint32_t msk_control; 2185165138Syongari}; 2186165138Syongari 2187165138Syongari/* Tx descriptor data structure */ 2188165138Syongaristruct msk_tx_desc { 2189165138Syongari uint32_t msk_addr; 2190165138Syongari uint32_t msk_control; 2191165138Syongari}; 2192165138Syongari 2193165138Syongari/* Status descriptor data structure */ 2194165138Syongaristruct msk_stat_desc { 2195165138Syongari uint32_t msk_status; 2196165138Syongari uint32_t msk_control; 2197165138Syongari}; 2198165138Syongari 2199165138Syongari/* mask and shift value to get Tx async queue status for port 1 */ 2200165138Syongari#define STLE_TXA1_MSKL 0x00000fff 2201165138Syongari#define STLE_TXA1_SHIFTL 0 2202165138Syongari 2203165138Syongari/* mask and shift value to get Tx sync queue status for port 1 */ 2204165138Syongari#define STLE_TXS1_MSKL 0x00fff000 2205165138Syongari#define STLE_TXS1_SHIFTL 12 2206165138Syongari 2207165138Syongari/* mask and shift value to get Tx async queue status for port 2 */ 2208165138Syongari#define STLE_TXA2_MSKL 0xff000000 2209165138Syongari#define STLE_TXA2_SHIFTL 24 2210165138Syongari#define STLE_TXA2_MSKH 0x000f 2211165138Syongari/* this one shifts up */ 2212165138Syongari#define STLE_TXA2_SHIFTH 8 2213165138Syongari 2214165138Syongari/* mask and shift value to get Tx sync queue status for port 2 */ 2215165138Syongari#define STLE_TXS2_MSKL 0x00000000 2216165138Syongari#define STLE_TXS2_SHIFTL 0 2217165138Syongari#define STLE_TXS2_MSKH 0xfff0 2218165138Syongari#define STLE_TXS2_SHIFTH 4 2219165138Syongari 2220165138Syongari/* YUKON-2 bit values */ 2221165138Syongari#define HW_OWNER 0x80000000 2222165138Syongari#define SW_OWNER 0x00000000 2223165138Syongari 2224165138Syongari#define PU_PUTIDX_VALID 0x10000000 2225165138Syongari 2226165138Syongari/* YUKON-2 Control flags */ 2227165138Syongari#define UDPTCP 0x00010000 2228165138Syongari#define CALSUM 0x00020000 2229165138Syongari#define WR_SUM 0x00040000 2230165138Syongari#define INIT_SUM 0x00080000 2231165138Syongari#define LOCK_SUM 0x00100000 2232165138Syongari#define INS_VLAN 0x00200000 2233165138Syongari#define FRC_STAT 0x00400000 2234165138Syongari#define EOP 0x00800000 2235165138Syongari 2236165138Syongari#define TX_LOCK 0x01000000 2237165138Syongari#define BUF_SEND 0x02000000 2238165138Syongari#define PACKET_SEND 0x04000000 2239165138Syongari 2240165138Syongari#define NO_WARNING 0x40000000 2241165138Syongari#define NO_UPDATE 0x80000000 2242165138Syongari 2243165138Syongari/* YUKON-2 Rx/Tx opcodes defines */ 2244165138Syongari#define OP_TCPWRITE 0x11000000 2245165138Syongari#define OP_TCPSTART 0x12000000 2246165138Syongari#define OP_TCPINIT 0x14000000 2247165138Syongari#define OP_TCPLCK 0x18000000 2248165138Syongari#define OP_TCPCHKSUM OP_TCPSTART 2249165138Syongari#define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) 2250165138Syongari#define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) 2251165138Syongari#define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) 2252165138Syongari#define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) 2253165138Syongari#define OP_ADDR64 0x21000000 2254165138Syongari#define OP_VLAN 0x22000000 2255165138Syongari#define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) 2256165138Syongari#define OP_LRGLEN 0x24000000 2257165138Syongari#define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) 2258192726Syongari#define OP_MSS 0x28000000 2259192726Syongari#define OP_MSSVLAN (OP_MSS | OP_VLAN) 2260165138Syongari#define OP_BUFFER 0x40000000 2261165138Syongari#define OP_PACKET 0x41000000 2262165138Syongari#define OP_LARGESEND 0x43000000 2263165138Syongari 2264165138Syongari/* YUKON-2 STATUS opcodes defines */ 2265165138Syongari#define OP_RXSTAT 0x60000000 2266165138Syongari#define OP_RXTIMESTAMP 0x61000000 2267165138Syongari#define OP_RXVLAN 0x62000000 2268165138Syongari#define OP_RXCHKS 0x64000000 2269165138Syongari#define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) 2270165138Syongari#define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) 2271165138Syongari#define OP_RSS_HASH 0x65000000 2272165138Syongari#define OP_TXINDEXLE 0x68000000 2273165138Syongari 2274165138Syongari/* YUKON-2 SPECIAL opcodes defines */ 2275165138Syongari#define OP_PUTIDX 0x70000000 2276165138Syongari 2277165138Syongari#define STLE_OP_MASK 0xff000000 2278193298Syongari#define STLE_CSS_MASK 0x00ff0000 2279165138Syongari#define STLE_LEN_MASK 0x0000ffff 2280165138Syongari 2281193298Syongari/* CSS defined in status LE(valid for descriptor V2 format). */ 2282193298Syongari#define CSS_TCPUDP_CSUM_OK 0x00800000 2283193298Syongari#define CSS_UDP 0x00400000 2284193298Syongari#define CSS_TCP 0x00200000 2285193298Syongari#define CSS_IPFRAG 0x00100000 2286193298Syongari#define CSS_IPV6 0x00080000 2287193298Syongari#define CSS_IPV4_CSUM_OK 0x00040000 2288193298Syongari#define CSS_IPV4 0x00020000 2289193298Syongari#define CSS_PORT 0x00010000 2290193298Syongari 2291165138Syongari/* Descriptor Bit Definition */ 2292165138Syongari/* TxCtrl Transmit Buffer Control Field */ 2293165138Syongari/* RxCtrl Receive Buffer Control Field */ 2294165138Syongari#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ 2295165138Syongari#define BMU_STF BIT_30 /* Start of Frame */ 2296165138Syongari#define BMU_EOF BIT_29 /* End of Frame */ 2297165138Syongari#define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ 2298165138Syongari#define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ 2299165138Syongari/* TxCtrl specific bits */ 2300165138Syongari#define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ 2301165138Syongari#define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ 2302165138Syongari#define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ 2303165138Syongari/* RxCtrl specific bits */ 2304165138Syongari#define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ 2305165138Syongari#define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ 2306165138Syongari#define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ 2307165138Syongari /* Bit 23..16: BMU Check Opcodes */ 2308165138Syongari#define BMU_CHECK (0x55<<16) /* Default BMU check */ 2309165138Syongari#define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ 2310165138Syongari#define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ 2311165138Syongari#define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ 2312165138Syongari 2313227582Syongari/* 2314227582Syongari * Controller requires an additional LE op code for 64bit DMA operation. 2315227582Syongari * Driver uses fixed number of RX buffers such that this limitation 2316227582Syongari * reduces number of available RX buffers with 64bit DMA so double 2317227582Syongari * number of RX buffers on platforms that support 64bit DMA. For TX 2318227582Syongari * side, controller requires an additional OP_ADDR64 op code if a TX 2319227582Syongari * buffer uses different high address value than previously used one. 2320227582Syongari * Driver monitors high DMA address change in TX and inserts an 2321227582Syongari * OP_ADDR64 op code if the high DMA address is changed. Driver 2322227582Syongari * allocates 50% more total TX buffers on platforms that support 64bit 2323227582Syongari * DMA. 2324227582Syongari */ 2325227582Syongari#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2326227582Syongari#define MSK_64BIT_DMA 2327227582Syongari#define MSK_TX_RING_CNT 384 2328227582Syongari#define MSK_RX_RING_CNT 512 2329227582Syongari#else 2330227582Syongari#undef MSK_64BIT_DMA 2331165138Syongari#define MSK_TX_RING_CNT 256 2332165138Syongari#define MSK_RX_RING_CNT 256 2333227582Syongari#endif 2334183346Syongari#define MSK_RX_BUF_ALIGN 8 2335165138Syongari#define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT 2336263957Syongari#define MSK_MAXTXSEGS 35 2337170523Syongari#define MSK_TSO_MAXSGSIZE 4096 2338170604Syongari#define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 2339165138Syongari 2340165138Syongari/* 2341227582Syongari * It seems that the hardware requires extra descriptors(LEs) to offload 2342227582Syongari * TCP/UDP checksum, VLAN hardware tag insertion and TSO. 2343165138Syongari * 2344165138Syongari * 1 descriptor for TCP/UDP checksum offload. 2345165138Syongari * 1 descriptor VLAN hardware tag insertion. 2346165138Syongari * 1 descriptor for TSO(TCP Segmentation Offload) 2347227582Syongari * 1 descriptor for each 64bits DMA transfers 2348165138Syongari */ 2349227582Syongari#ifdef MSK_64BIT_DMA 2350227582Syongari#define MSK_RESERVED_TX_DESC_CNT (MSK_MAXTXSEGS + 3) 2351227582Syongari#else 2352165138Syongari#define MSK_RESERVED_TX_DESC_CNT 3 2353227582Syongari#endif 2354165138Syongari 2355165138Syongari#define MSK_JUMBO_FRAMELEN 9022 2356165138Syongari#define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2357165138Syongari#define MSK_MAX_FRAMELEN \ 2358165138Syongari (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 2359165138Syongari#define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 2360165138Syongari 2361165138Syongaristruct msk_txdesc { 2362165138Syongari struct mbuf *tx_m; 2363165138Syongari bus_dmamap_t tx_dmamap; 2364165138Syongari struct msk_tx_desc *tx_le; 2365165138Syongari}; 2366165138Syongari 2367165138Syongaristruct msk_rxdesc { 2368165138Syongari struct mbuf *rx_m; 2369165138Syongari bus_dmamap_t rx_dmamap; 2370165138Syongari struct msk_rx_desc *rx_le; 2371165138Syongari}; 2372165138Syongari 2373165138Syongaristruct msk_chain_data { 2374165138Syongari bus_dma_tag_t msk_parent_tag; 2375165138Syongari bus_dma_tag_t msk_tx_tag; 2376165138Syongari struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT]; 2377165138Syongari bus_dma_tag_t msk_rx_tag; 2378165138Syongari struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT]; 2379165138Syongari bus_dma_tag_t msk_tx_ring_tag; 2380165138Syongari bus_dma_tag_t msk_rx_ring_tag; 2381165138Syongari bus_dmamap_t msk_tx_ring_map; 2382165138Syongari bus_dmamap_t msk_rx_ring_map; 2383165138Syongari bus_dmamap_t msk_rx_sparemap; 2384165138Syongari bus_dma_tag_t msk_jumbo_rx_tag; 2385165138Syongari struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]; 2386165138Syongari bus_dma_tag_t msk_jumbo_rx_ring_tag; 2387165138Syongari bus_dmamap_t msk_jumbo_rx_ring_map; 2388165138Syongari bus_dmamap_t msk_jumbo_rx_sparemap; 2389165138Syongari uint16_t msk_tso_mtu; 2390204363Syongari uint32_t msk_last_csum; 2391227582Syongari uint32_t msk_tx_high_addr; 2392165138Syongari int msk_tx_prod; 2393165138Syongari int msk_tx_cons; 2394165138Syongari int msk_tx_cnt; 2395165138Syongari int msk_tx_put; 2396165138Syongari int msk_rx_cons; 2397165138Syongari int msk_rx_prod; 2398165138Syongari int msk_rx_putwm; 2399165138Syongari}; 2400165138Syongari 2401165138Syongaristruct msk_ring_data { 2402165138Syongari struct msk_tx_desc *msk_tx_ring; 2403165138Syongari bus_addr_t msk_tx_ring_paddr; 2404165138Syongari struct msk_rx_desc *msk_rx_ring; 2405165138Syongari bus_addr_t msk_rx_ring_paddr; 2406165138Syongari struct msk_rx_desc *msk_jumbo_rx_ring; 2407165138Syongari bus_addr_t msk_jumbo_rx_ring_paddr; 2408165138Syongari}; 2409165138Syongari 2410165138Syongari#define MSK_TX_RING_ADDR(sc, i) \ 2411165138Syongari ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) 2412165138Syongari#define MSK_RX_RING_ADDR(sc, i) \ 2413165138Syongari ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2414165138Syongari#define MSK_JUMBO_RX_RING_ADDR(sc, i) \ 2415165138Syongari ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2416165138Syongari 2417165138Syongari#define MSK_TX_RING_SZ \ 2418165138Syongari (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) 2419165138Syongari#define MSK_RX_RING_SZ \ 2420165138Syongari (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) 2421165138Syongari#define MSK_JUMBO_RX_RING_SZ \ 2422165138Syongari (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) 2423165138Syongari 2424165138Syongari#define MSK_INC(x, y) (x) = (x + 1) % y 2425227582Syongari#ifdef MSK_64BIT_DMA 2426227582Syongari#define MSK_RX_INC(x, y) (x) = (x + 2) % y 2427227582Syongari#define MSK_RX_BUF_CNT (MSK_RX_RING_CNT / 2) 2428227582Syongari#define MSK_JUMBO_RX_BUF_CNT (MSK_JUMBO_RX_RING_CNT / 2) 2429227582Syongari#else 2430227582Syongari#define MSK_RX_INC(x, y) (x) = (x + 1) % y 2431227582Syongari#define MSK_RX_BUF_CNT MSK_RX_RING_CNT 2432227582Syongari#define MSK_JUMBO_RX_BUF_CNT MSK_JUMBO_RX_RING_CNT 2433227582Syongari#endif 2434165138Syongari 2435165138Syongari#define MSK_PCI_BUS 0 2436165138Syongari#define MSK_PCIX_BUS 1 2437165138Syongari#define MSK_PEX_BUS 2 2438165138Syongari 2439165138Syongari#define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) 2440165138Syongari#define MSK_PROC_MIN 30 2441165138Syongari#define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) 2442165138Syongari 2443204541Syongari#define MSK_INT_HOLDOFF_DEFAULT 100 2444204541Syongari 2445165138Syongari#define MSK_TX_TIMEOUT 5 2446165138Syongari#define MSK_PUT_WM 10 2447165138Syongari 2448197590Syongaristruct msk_mii_data { 2449197590Syongari int port; 2450197590Syongari uint32_t pmd; 2451197590Syongari int mii_flags; 2452197590Syongari}; 2453197590Syongari 2454165138Syongari/* Forward decl. */ 2455165138Syongaristruct msk_if_softc; 2456165138Syongari 2457187325Syongaristruct msk_hw_stats { 2458187325Syongari /* Rx stats. */ 2459187325Syongari uint32_t rx_ucast_frames; 2460187325Syongari uint32_t rx_bcast_frames; 2461187325Syongari uint32_t rx_pause_frames; 2462187325Syongari uint32_t rx_mcast_frames; 2463187325Syongari uint32_t rx_crc_errs; 2464187325Syongari uint32_t rx_spare1; 2465187325Syongari uint64_t rx_good_octets; 2466187325Syongari uint64_t rx_bad_octets; 2467187325Syongari uint32_t rx_runts; 2468187325Syongari uint32_t rx_runt_errs; 2469187325Syongari uint32_t rx_pkts_64; 2470187325Syongari uint32_t rx_pkts_65_127; 2471187325Syongari uint32_t rx_pkts_128_255; 2472187325Syongari uint32_t rx_pkts_256_511; 2473187325Syongari uint32_t rx_pkts_512_1023; 2474187325Syongari uint32_t rx_pkts_1024_1518; 2475187325Syongari uint32_t rx_pkts_1519_max; 2476187325Syongari uint32_t rx_pkts_too_long; 2477187325Syongari uint32_t rx_pkts_jabbers; 2478187325Syongari uint32_t rx_spare2; 2479187325Syongari uint32_t rx_fifo_oflows; 2480187325Syongari uint32_t rx_spare3; 2481187325Syongari /* Tx stats. */ 2482187325Syongari uint32_t tx_ucast_frames; 2483187325Syongari uint32_t tx_bcast_frames; 2484187325Syongari uint32_t tx_pause_frames; 2485187325Syongari uint32_t tx_mcast_frames; 2486187325Syongari uint64_t tx_octets; 2487187325Syongari uint32_t tx_pkts_64; 2488187325Syongari uint32_t tx_pkts_65_127; 2489187325Syongari uint32_t tx_pkts_128_255; 2490187325Syongari uint32_t tx_pkts_256_511; 2491187325Syongari uint32_t tx_pkts_512_1023; 2492187325Syongari uint32_t tx_pkts_1024_1518; 2493187325Syongari uint32_t tx_pkts_1519_max; 2494187325Syongari uint32_t tx_spare1; 2495187325Syongari uint32_t tx_colls; 2496187325Syongari uint32_t tx_late_colls; 2497187325Syongari uint32_t tx_excess_colls; 2498187325Syongari uint32_t tx_multi_colls; 2499187325Syongari uint32_t tx_single_colls; 2500187325Syongari uint32_t tx_underflows; 2501187325Syongari}; 2502187325Syongari 2503165138Syongari/* Softc for the Marvell Yukon II controller. */ 2504165138Syongaristruct msk_softc { 2505165611Syongari struct resource *msk_res[1]; /* I/O resource */ 2506165138Syongari struct resource_spec *msk_res_spec; 2507204366Syongari struct resource *msk_irq[1]; /* IRQ resources */ 2508165611Syongari struct resource_spec *msk_irq_spec; 2509204366Syongari void *msk_intrhand; /* irq handler handle */ 2510165138Syongari device_t msk_dev; 2511165138Syongari uint8_t msk_hw_id; 2512165138Syongari uint8_t msk_hw_rev; 2513165138Syongari uint8_t msk_bustype; 2514165138Syongari uint8_t msk_num_port; 2515204365Syongari int msk_expcap; 2516204365Syongari int msk_pcixcap; 2517165138Syongari int msk_ramsize; /* amount of SRAM on NIC */ 2518165138Syongari uint32_t msk_pmd; /* physical media type */ 2519165138Syongari uint32_t msk_intrmask; 2520165138Syongari uint32_t msk_intrhwemask; 2521183346Syongari uint32_t msk_pflags; 2522165138Syongari int msk_clock; 2523165138Syongari struct msk_if_softc *msk_if[2]; 2524165138Syongari device_t msk_devs[2]; 2525165138Syongari int msk_txqsize; 2526165138Syongari int msk_rxqsize; 2527165138Syongari int msk_txqstart[2]; 2528165138Syongari int msk_txqend[2]; 2529165138Syongari int msk_rxqstart[2]; 2530165138Syongari int msk_rxqend[2]; 2531165138Syongari bus_dma_tag_t msk_stat_tag; 2532165138Syongari bus_dmamap_t msk_stat_map; 2533165138Syongari struct msk_stat_desc *msk_stat_ring; 2534165138Syongari bus_addr_t msk_stat_ring_paddr; 2535204541Syongari int msk_int_holdoff; 2536165138Syongari int msk_process_limit; 2537165138Syongari int msk_stat_cons; 2538227582Syongari int msk_stat_count; 2539165138Syongari struct mtx msk_mtx; 2540165138Syongari}; 2541165138Syongari 2542165138Syongari#define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) 2543165138Syongari#define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) 2544165138Syongari#define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) 2545165138Syongari#define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) 2546165138Syongari#define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) 2547165138Syongari#define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) 2548165138Syongari 2549165138Syongari#define MSK_USECS(sc, us) ((sc)->msk_clock * (us)) 2550165138Syongari 2551165138Syongari/* Softc for each logical interface. */ 2552165138Syongaristruct msk_if_softc { 2553165138Syongari struct ifnet *msk_ifp; /* interface info */ 2554165138Syongari device_t msk_miibus; 2555165138Syongari device_t msk_if_dev; 2556165138Syongari int32_t msk_port; /* port # on controller */ 2557165138Syongari int msk_framesize; 2558165138Syongari int msk_phytype; 2559165138Syongari int msk_phyaddr; 2560183346Syongari uint32_t msk_flags; 2561192719Syongari#define MSK_FLAG_MSI 0x0001 2562192723Syongari#define MSK_FLAG_FASTETHER 0x0004 2563192723Syongari#define MSK_FLAG_JUMBO 0x0008 2564192723Syongari#define MSK_FLAG_JUMBO_NOCSUM 0x0010 2565192723Syongari#define MSK_FLAG_RAMBUF 0x0020 2566192726Syongari#define MSK_FLAG_DESCV2 0x0040 2567193294Syongari#define MSK_FLAG_AUTOTX_CSUM 0x0080 2568193294Syongari#define MSK_FLAG_NOHWVLAN 0x0100 2569193294Syongari#define MSK_FLAG_NORXCHK 0x0200 2570193298Syongari#define MSK_FLAG_NORX_CSUM 0x0400 2571192718Syongari#define MSK_FLAG_SUSPEND 0x2000 2572192719Syongari#define MSK_FLAG_DETACH 0x4000 2573192718Syongari#define MSK_FLAG_LINK 0x8000 2574165138Syongari struct callout msk_tick_ch; 2575165613Syongari int msk_watchdog_timer; 2576165138Syongari uint32_t msk_txq; /* Tx. Async Queue offset */ 2577165138Syongari uint32_t msk_txsq; /* Tx. Syn Queue offset */ 2578165138Syongari uint32_t msk_rxq; /* Rx. Qeueue offset */ 2579165138Syongari struct msk_chain_data msk_cdata; 2580165138Syongari struct msk_ring_data msk_rdata; 2581165138Syongari struct msk_softc *msk_softc; /* parent controller */ 2582187325Syongari struct msk_hw_stats msk_stats; 2583165138Syongari int msk_if_flags; 2584165138Syongari uint16_t msk_vtag; /* VLAN tag id. */ 2585205091Syongari uint32_t msk_csum; 2586165138Syongari}; 2587165138Syongari 2588165138Syongari#define MSK_TIMEOUT 1000 2589165138Syongari#define MSK_PHY_POWERUP 1 2590165138Syongari#define MSK_PHY_POWERDOWN 0 2591