Searched refs:getOpcode (Results 151 - 175 of 780) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLateEHPrepare.cpp153 switch (TI->getOpcode()) {
189 if (MI.getOpcode() != WebAssembly::THROW &&
190 MI.getOpcode() != WebAssembly::RETHROW)
243 if (MI.getOpcode() == WebAssembly::EXTRACT_EXCEPTION_I32) {
385 if (InsertPos->getOpcode() == WebAssembly::CATCH)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp78 dbgs() << Instruction::getOpcodeName(I->getOpcode()) << " "
124 if (I && (I->getOpcode() == Instruction::Or ||
125 I->getOpcode() == Instruction::And)) {
135 isOr = (I->getOpcode() == Instruction::Or);
150 if (I && I->hasOneUse() && I->getOpcode() == Opcode)
160 (I->getOpcode() == Opcode1 || I->getOpcode() == Opcode2))
458 unsigned Opcode = I->getOpcode();
574 cast<Instruction>(Op)->getOpcode() != Opcode
651 unsigned Opcode = I->getOpcode();
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H A DSeparateConstOffsetFromGEP.cpp491 if (BO->getOpcode() != Instruction::Add &&
492 BO->getOpcode() != Instruction::Sub &&
493 BO->getOpcode() != Instruction::Or) {
502 if (BO->getOpcode() == Instruction::Or &&
517 if (BO->getOpcode() == Instruction::Add && !ZeroExtended && NonNegative) {
538 if (BO->getOpcode() == Instruction::Add ||
539 BO->getOpcode() == Instruction::Sub) {
566 if (BO->getOpcode() == Instruction::Sub)
623 Current = ConstantExpr::getCast((*I)->getOpcode(), C, (*I)->getType());
675 NewBO = BinaryOperator::Create(BO->getOpcode(), NextInChai
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp167 unsigned Opc = I->getOpcode();
241 switch (MI.getOpcode()) {
289 switch (MI.getOpcode()) {
427 bool JumpToBlock = I->getOpcode() == Hexagon::J2_jump &&
459 int LastOpcode = LastInst->getOpcode();
460 int SecLastOpcode = SecondLastInst ? SecondLastInst->getOpcode() : 0;
483 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
489 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
496 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
513 Cond.push_back(MachineOperand::CreateImm(SecondLastInst->getOpcode()));
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H A DHexagonInstrInfo.h494 return changeAddrMode_abs_io(MI.getOpcode());
497 return changeAddrMode_io_abs(MI.getOpcode());
500 return changeAddrMode_io_rr(MI.getOpcode());
503 return changeAddrMode_rr_io(MI.getOpcode());
506 return changeAddrMode_rr_ur(MI.getOpcode());
509 return changeAddrMode_ur_rr(MI.getOpcode());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp185 bool IsDo = Start->getOpcode() == ARM::t2DoLoopStart;
189 return VCTPOpcodeToLSTP(VCTP->getOpcode(), IsDo);
271 return MI->getOpcode() == ARM::tMOVr &&
452 if (Start->getOpcode() == ARM::t2WhileLoopStart &&
492 if (MI->getOpcode() == ARM::MVE_VPST) {
498 else if (MI->getOpcode() == ARM::MVE_VPSEL ||
499 MI->getOpcode() == ARM::MVE_VPNOT)
627 if (MI.getOpcode() == ARM::t2LoopDec)
629 else if (MI.getOpcode() == ARM::t2LoopEnd)
659 if (MI.getOpcode() !
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H A DARMISelDAGToDAG.cpp329 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
346 return N->getOpcode() == Opc &&
381 if (N->getOpcode() != ISD::ADD)
469 if (Use->getOpcode() == ISD::CopyToReg)
478 unsigned Opcode = MCID.getOpcode();
516 assert(N.getOpcode() == ISD::MUL);
560 if (N.getOpcode() == ISD::MUL) {
574 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
598 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
620 assert(Parent->getOpcode()
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H A DThumb2SizeReduction.cpp263 switch(Def->getOpcode()) {
323 if (Use->getOpcode() == ARM::t2MOVi ||
324 Use->getOpcode() == ARM::t2MOVi16)
375 unsigned Opc = MI->getOpcode();
625 unsigned Opc = MI->getOpcode();
749 if (MI->getOpcode() == ARM::t2MUL) {
920 if (MCID.getOpcode() == ARM::t2TEQrr) {
940 if ((MCID.getOpcode() == ARM::t2RSBSri ||
941 MCID.getOpcode() == ARM::t2RSBri ||
942 MCID.getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp48 switch (N->getOpcode()) {
230 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
242 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N),
255 assert(N->getOpcode() == ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
291 N->getOpcode(), SDLoc(N), N->getMemoryVT(), VTs, N->getChain(),
465 Op = DAG.getNode(N->getOpcode(), dl, NVT, Op);
484 if (N->getOpcode() == ISD::CTTZ) {
492 return DAG.getNode(N->getOpcode(), dl, NVT, Op);
522 unsigned NewOpc = N->getOpcode();
529 if (N->getOpcode()
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H A DTargetLowering.cpp94 if (Value->getOpcode() != ISD::CopyFromReg)
497 unsigned Opcode = Op.getOpcode();
569 Op.getOpcode(), dl, SmallVT,
627 switch (Op.getOpcode()) {
784 if (Op.getOpcode() >= ISD::BUILTIN_OP_END)
825 if (Op.getOpcode() == ISD::Constant) {
854 switch (Op.getOpcode()) {
1105 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1154 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op0, Op1);
1200 SDValue NewOp = TLO.DAG.getNode(Op.getOpcode(), d
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H A DLegalizeVectorTypes.cpp40 switch (N->getOpcode()) {
182 return DAG.getNode(N->getOpcode(), SDLoc(N),
190 return DAG.getNode(N->getOpcode(), SDLoc(N),
198 return DAG.getNode(N->getOpcode(), SDLoc(N), Op0.getValueType(), Op0, Op1,
224 SDValue Result = DAG.getNode(N->getOpcode(), dl, ValueVTs, Opers);
253 N->getOpcode(), DL, ScalarVTs, ScalarLHS, ScalarRHS).getNode();
364 return DAG.getNode(N->getOpcode(), SDLoc(N), DestVT, Op);
371 return DAG.getNode(N->getOpcode(), SDLoc(N), EltVT,
391 switch (N->getOpcode()) {
442 if (Cond->getOpcode()
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H A DLegalizeDAG.cpp677 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
698 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
963 if (Node->getOpcode() == ISD::TargetConstant ||
964 Node->getOpcode() == ISD::Register)
976 Op.getOpcode() == ISD::TargetConstant ||
977 Op.getOpcode() == ISD::Register) &&
984 switch (Node->getOpcode()) {
989 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
992 Action = TLI.getOperationAction(Node->getOpcode(),
996 Action = TLI.getOperationAction(Node->getOpcode(),
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H A DLegalizeVectorOps.cpp258 if (Op.getOpcode() == ISD::LOAD) {
289 } else if (Op.getOpcode() == ISD::STORE) {
332 switch (Op.getOpcode()) {
336 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
346 if (Op.getOpcode() == ISD::STRICT_SINT_TO_FP ||
347 Op.getOpcode() == ISD::STRICT_UINT_TO_FP)
349 Action = TLI.getOperationAction(Node->getOpcode(), ValVT);
356 TLI.getStrictFPOperationAction(Node->getOpcode(), ValVT) ==
359 if (TLI.getOperationAction(Node->getOpcode(), EltVT)
361 TLI.getStrictFPOperationAction(Node->getOpcode(), EltV
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FloatingPoint.cpp846 int Opcode = Lookup(PopTable, I->getOpcode());
1109 MI.setDesc(TII->get(getConcreteOpcode(MI.getOpcode())));
1135 if (!KillsSrc && (MI.getOpcode() == X86::IST_Fp64m32 ||
1136 MI.getOpcode() == X86::ISTT_Fp16m32 ||
1137 MI.getOpcode() == X86::ISTT_Fp32m32 ||
1138 MI.getOpcode() == X86::ISTT_Fp64m32 ||
1139 MI.getOpcode() == X86::IST_Fp64m64 ||
1140 MI.getOpcode() == X86::ISTT_Fp16m64 ||
1141 MI.getOpcode() == X86::ISTT_Fp32m64 ||
1142 MI.getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp84 switch (MI.getOpcode()) {
103 switch (MI.getOpcode()) {
293 if (I->getOpcode() == AVR::RJMPk) {
324 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
352 unsigned JNCC = getBrCond(BranchCode).getOpcode();
451 if (I->getOpcode() != AVR::RJMPk &&
452 getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
477 unsigned Opcode = MI.getOpcode();
505 switch (MI.getOpcode()) {
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Transforms/Scalar/
H A DGVNExpression.h78 if (getOpcode() != Other.getOpcode())
80 if (getOpcode() == getEmptyKey() || getOpcode() == getTombstoneKey())
108 unsigned getOpcode() const { return Opcode; } function in class:llvm::GVNExpression::Expression
113 virtual hash_code getHashValue() const { return getOpcode(); }
119 OS << "opcode = " << getOpcode() << ", ";
214 if (getOpcode() != Other.getOpcode())
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DEvaluator.cpp85 switch (CE->getOpcode()) {
143 if (CE->getOpcode() == Instruction::GetElementPtr &&
166 } else if (CE->getOpcode() == Instruction::BitCast &&
232 switch (CE->getOpcode()) {
276 if (!CE || CE->getOpcode() != Instruction::BitCast ||
313 if (!RV || !CE || CE->getOpcode() != Instruction::BitCast)
365 if (CE->getOpcode() == Instruction::BitCast) {
399 InstResult = ConstantExpr::get(BO->getOpcode(),
411 InstResult = ConstantExpr::getCast(CI->getOpcode(),
H A DBypassSlowDivision.cpp93 return SlowDivOrRem->getOpcode() == Instruction::SDiv ||
94 SlowDivOrRem->getOpcode() == Instruction::SRem;
98 return SlowDivOrRem->getOpcode() == Instruction::SDiv ||
99 SlowDivOrRem->getOpcode() == Instruction::UDiv;
114 switch (I->getOpcode()) {
195 switch (I->getOpcode()) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp403 auto DstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
417 if ((MI.getOpcode() == AMDGPU::V_FMAC_F16_sdwa ||
418 MI.getOpcode() == AMDGPU::V_FMAC_F32_sdwa ||
419 MI.getOpcode() == AMDGPU::V_MAC_F16_sdwa ||
420 MI.getOpcode() == AMDGPU::V_MAC_F32_sdwa) &&
461 if ((MI.getOpcode() == AMDGPU::V_FMAC_F16_sdwa ||
462 MI.getOpcode() == AMDGPU::V_FMAC_F32_sdwa ||
463 MI.getOpcode() == AMDGPU::V_MAC_F16_sdwa ||
464 MI.getOpcode() == AMDGPU::V_MAC_F32_sdwa) &&
511 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGP
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H A DR600OptimizeVectorRegisters.cpp76 assert(MI->getOpcode() == R600::REG_SEQUENCE);
153 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
155 switch (MI.getOpcode()) {
267 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST)
351 if (MI.getOpcode() != R600::REG_SEQUENCE) {
352 if (TII->get(MI.getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelDAGToDAG.cpp88 if ((MI.getOpcode() == Mips::ADDiu) &&
94 } else if ((MI.getOpcode() == Mips::DADDiu) &&
162 switch (MI.getOpcode()) {
208 unsigned Opc = InFlag.getOpcode();
319 if (Addr.getOpcode() == MipsISD::Wrapper) {
326 if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
327 Addr.getOpcode() == ISD::TargetGlobalAddress))
336 if (Addr.getOpcode() == ISD::ADD) {
345 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
346 Addr.getOperand(1).getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp226 if (N.getOpcode() == ISD::TargetConstant ||
227 N.getOpcode() == ISD::TargetGlobalAddress) {
486 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
496 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
570 return N->getOpcode() == Opc
597 unsigned Opcode = N->getOpcode();
631 if (Base.getOpcode() != PPCISD::ADD_TLS)
674 if (Base.getOpcode() != PPCISD::ADD_TLS)
727 unsigned Op0Opc = Op0.getOpcode();
728 unsigned Op1Opc = Op1.getOpcode();
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCDuplexInfo.cpp193 switch (MCI.getOpcode()) {
543 switch (potentialDuplex.getOpcode()) {
588 unsigned Opcode = MIb.getOpcode();
605 subinstOpcodeMap.find(SubInst0.getOpcode())->second;
607 subinstOpcodeMap.find(SubInst1.getOpcode())->second;
616 if (MIb.getOpcode() == Hexagon::S2_allocframe)
706 switch (Inst.getOpcode()) {
708 // dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
1050 if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) &&
1051 isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp141 switch(N->getOpcode()) {
302 return N->getOpcode() == Opc &&
396 switch (N.getOpcode()) {
413 assert(V.getOpcode() == ISD::SHL && "invalid opcode");
442 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::SHL &&
445 if (Subtarget->hasLSLFast() && V.getOpcode() == ISD::ADD) {
448 if (LHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(LHS))
450 if (RHS.getOpcode() == ISD::SHL && isWorthFoldingSHL(RHS))
488 if (N.getOpcode() == ISD::SIGN_EXTEND ||
489 N.getOpcode()
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp614 assert ((I == nullptr || I->getOpcode() == Opcode) &&
637 assert ((I == nullptr || I->getOpcode() == Opcode) &&
655 assert ((I == nullptr || I->getOpcode() == Opcode) &&
907 return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
916 return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
921 return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
1155 switch (I->getOpcode()) {
1162 return getCFInstrCost(I->getOpcode());
1187 return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1197 return getArithmeticInstrCost(I->getOpcode(),
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