/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/ |
H A D | MachineCopyPropagation.cpp | 99 void markRegsUnavailable(ArrayRef<unsigned> Regs, argument 101 for (unsigned Reg : Regs) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 2426 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, 2443 Inst.addOperand(MCOperand::createReg(Regs[i])); 2454 unsigned Regs[] = {Mips::S0, Mips::S1, Mips::S2, Mips::S3}; local 2468 Inst.addOperand(MCOperand::createReg(Regs[i]));
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | CodeGenRegisters.h | 773 // Compute the set of registers completely covered by the registers in Regs. 774 // The returned BitVector will have a bit set for each register in Regs, 776 // registers in Regs. 780 BitVector computeCoveredRegisters(ArrayRef<Record*> Regs);
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H A D | AsmMatcherEmitter.cpp | 2599 const auto &Regs = Target.getRegBank().getRegisters(); 2600 for (const CodeGenRegister &Reg : Regs) { 2624 const auto &Regs = Target.getRegBank().getRegisters(); 2625 for (const CodeGenRegister &Reg : Regs) {
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPURegisterBankInfo.cpp | 677 SmallVector<Register, 2> &Regs, 688 Regs.push_back(LoLHS); 689 Regs.push_back(HiLHS); 697 /// Replace the current type each register in \p Regs has with \p NewTy 698 static void setRegsToType(MachineRegisterInfo &MRI, ArrayRef<Register> Regs, argument 700 for (Register Reg : Regs) { 675 split64BitValueForMapping( MachineIRBuilder &B, SmallVector<Register, 2> &Regs, LLT HalfTy, Register Reg) const argument
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H A D | SIInstrInfo.cpp | 2242 SmallVector<unsigned, 8> Regs; local 2245 Regs.push_back(DstElt);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FrameLowering.cpp | 2738 unsigned Regs[2]; 2771 Regs[FoundRegs++] = Candidate; 2781 Regs[FoundRegs++] = Regs[0]; 2785 TII.get(STI.is64Bit() ? X86::POP64r : X86::POP32r), Regs[i]);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonBitSimplify.cpp | 1015 SmallVector<unsigned,2> Regs; 1024 Regs.push_back(R); 1030 for (unsigned i = 0, n = Regs.size(); i != n; ++i) 1031 MRI.markUsesInDebugValueAsUndef(Regs[i]);
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H A D | HexagonInstrInfo.cpp | 969 static void getLiveRegsAt(LivePhysRegs &Regs, const MachineInstr &MI) { argument 971 Regs.addLiveOuts(B); 974 Regs.stepBackward(*I);
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 3534 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, argument 3536 assert(Regs.size() > 0 && "RegList contains no registers?"); 3540 Regs.front().second)) { 3541 if (Regs.back().second == ARM::VPR) 3546 Regs.front().second)) { 3547 if (Regs.back().second == ARM::VPR) 3553 if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) 3556 assert(std::is_sorted(Regs.begin(), Regs.end()) && 3560 for (const auto &P : Regs) 4265 insertNoDuplicates(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs, unsigned Enc, unsigned Reg) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 1571 CreateRegList(SmallVectorImpl<unsigned> &Regs, SMLoc StartLoc, SMLoc EndLoc, argument 1573 assert(Regs.size() > 0 && "Empty list not allowed"); 1576 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end()); 6592 SmallVector<unsigned, 10> Regs; local 6611 Regs.push_back(RegNo); 6623 Regs.push_back(TmpReg++); 6650 Regs.push_back(RegNo); 6670 Operands.push_back(MipsOperand::CreateRegList(Regs, S, E, *this));
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 2519 const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, 2524 if (std::any_of(std::begin(Regs), std::end(Regs), [&STI](auto Reg) { 2518 validateCCReservedRegs( const SmallVectorImpl<std::pair<llvm::Register, llvm::SDValue>> &Regs, MachineFunction &MF) const argument
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