Searched refs:RD (Results 26 - 50 of 206) sorted by relevance

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/freebsd-11-stable/contrib/binutils/opcodes/
H A Dsparc-opc.c190 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 },
191 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
192 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 },
193 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 },
194 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
195 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
295 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },
296 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~
[all...]
/freebsd-11-stable/contrib/llvm-project/clang/lib/CodeGen/
H A DCGRecordLayoutBuilder.cpp83 const CXXRecordDecl *RD; member in union:__anon508::CGRecordLowering::MemberInfo::__anon509
89 const CXXRecordDecl *RD)
90 : Offset(Offset), Kind(Kind), Data(Data), RD(RD) {}
142 llvm::Type *getStorageType(const CXXRecordDecl *RD) { argument
143 return Types.getCGRecordLayout(RD).getBaseSubobjectLLVMType();
157 bool isZeroInitializable(const RecordDecl *RD) { argument
158 return Types.isZeroInitializable(RD);
196 const CXXRecordDecl *RD; member in struct:__anon508::CGRecordLowering
219 RD(dyn_cas
88 MemberInfo(CharUnits Offset, InfoKind Kind, llvm::Type *Data, const CXXRecordDecl *RD) argument
874 const RecordDecl *RD = it->first->getParent(); local
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H A DCGCXXABI.h140 virtual RecordArgABI getRecordArgABI(const CXXRecordDecl *RD) const = 0;
235 /// Determine whether it's possible to emit a vtable for \p RD, even
238 virtual bool canSpeculativelyEmitVTable(const CXXRecordDecl *RD) const = 0;
279 const CXXRecordDecl *RD);
285 const CXXRecordDecl *RD) {}
385 const CXXRecordDecl *RD) = 0;
403 getVTableAddressPointInStructor(CodeGenFunction &CGF, const CXXRecordDecl *RD,
414 /// used for the vptr at the given offset in RD.
415 virtual llvm::GlobalVariable *getAddrOfVTable(const CXXRecordDecl *RD,
441 virtual void emitVirtualInheritanceTables(const CXXRecordDecl *RD)
284 initializeHiddenVirtualInheritanceMembers(CodeGenFunction &CGF, const CXXRecordDecl *RD) argument
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H A DCGCXXABI.cpp50 const auto *RD = local
53 CGM.getTypes().arrangeCXXMethodType(RD, FPT, /*FD=*/nullptr));
259 const CXXRecordDecl *RD = cast<CXXRecordDecl>(MPD->getDeclContext()); local
261 const CXXRecordDecl *Base = RD;
267 RD = Path[I];
276 const CXXRecordDecl *RD) {
313 std::vector<CharUnits> CGCXXABI::getVBPtrOffsets(const CXXRecordDecl *RD) { argument
275 EmitCtorCompleteObjectHandler(CodeGenFunction &CGF, const CXXRecordDecl *RD) argument
H A DCodeGenTypes.h128 CanQualType DeriveThisType(const CXXRecordDecl *RD, const CXXMethodDecl *MD);
168 void RefreshTypeCacheForClass(const CXXRecordDecl *RD);
256 const CGFunctionInfo &arrangeCXXMethodType(const CXXRecordDecl *RD,
280 void addRecordTypeName(const RecordDecl *RD, llvm::StructType *Ty,
303 bool isZeroInitializable(const RecordDecl *RD);
H A DItaniumCXXABI.cpp70 RecordArgABI getRecordArgABI(const CXXRecordDecl *RD) const override {
72 if (!RD->canPassInRegisters())
171 void EmitFundamentalRTTIDescriptors(const CXXRecordDecl *RD);
236 const CXXRecordDecl *RD) override;
261 llvm::GlobalVariable *getAddrOfVTable(const CXXRecordDecl *RD,
273 void emitVirtualInheritanceTables(const CXXRecordDecl *RD) override;
275 bool canSpeculativelyEmitVTable(const CXXRecordDecl *RD) const override;
276 bool canSpeculativelyEmitVTableAsBaseClass(const CXXRecordDecl *RD) const;
407 const CXXRecordDecl *RD) override;
410 bool hasAnyUnusedVirtualInlineFunction(const CXXRecordDecl *RD) cons
600 auto *RD = local
756 CXXRecordDecl *RD = MPT->getClass()->getAsCXXRecordDecl(); local
1165 const CXXRecordDecl *RD = FI.getReturnType()->getAsCXXRecordDecl(); local
1650 emitVTableDefinitions(CodeGenVTables &CGVT, const CXXRecordDecl *RD) argument
1757 getAddrOfVTable(const CXXRecordDecl *RD, CharUnits VPtrOffset) argument
1860 emitVirtualInheritanceTables(const CXXRecordDecl *RD) argument
2918 const CXXRecordDecl *RD = Ty->getAsCXXRecordDecl(); local
3073 const CXXRecordDecl *RD = cast<CXXRecordDecl>(RecordTy->getDecl()); local
3143 CanUseSingleInheritance(const CXXRecordDecl *RD) argument
3233 const CXXRecordDecl *RD = local
3328 const CXXRecordDecl *RD = cast<CXXRecordDecl>(Record->getDecl()); local
3390 auto RD = Ty->getAsCXXRecordDecl(); local
3477 const CXXRecordDecl *RD = local
3598 BuildSIClassTypeInfo(const CXXRecordDecl *RD) argument
3656 ComputeVMIClassTypeInfoFlags(const CXXRecordDecl *RD) argument
3670 BuildVMIClassTypeInfo(const CXXRecordDecl *RD) argument
3841 EmitFundamentalRTTIDescriptors(const CXXRecordDecl *RD) argument
4392 LoadVTablePtr(CodeGenFunction &CGF, Address This, const CXXRecordDecl *RD) argument
[all...]
H A DModuleBuilder.cpp260 if (const RecordDecl *RD = dyn_cast<RecordDecl>(D))
261 DI->completeRequiredType(RD);
279 void AssignInheritanceModel(CXXRecordDecl *RD) override {
283 Builder->RefreshTypeCacheForClass(RD);
297 void HandleVTable(CXXRecordDecl *RD) override {
301 Builder->EmitVTable(RD);
H A DCGDebugInfo.cpp306 StringRef CGDebugInfo::getClassName(const RecordDecl *RD) { argument
307 if (isa<ClassTemplateSpecializationDecl>(RD)) {
312 RD->getNameForDiagnostic(OS, PP,
321 if (const IdentifierInfo *II = RD->getIdentifier())
327 if (const TypedefNameDecl *D = RD->getTypedefNameForAnonDecl()) {
328 assert(RD->getDeclContext() == D->getDeclContext() &&
339 if (const DeclaratorDecl *DD = Context.getDeclaratorForUnnamedTagDecl(RD))
344 Context.getTypedefNameForUnnamedTagDecl(RD))
937 if (const auto *RD = dyn_cast<CXXRecordDecl>(TD))
938 if (RD
951 getTagForRecord(const RecordDecl *RD) argument
969 const RecordDecl *RD = Ty->getDecl(); local
1215 getAccessFlag(AccessSpecifier Access, const RecordDecl *RD) argument
1239 createBitFieldType(const FieldDecl *BitFieldDecl, llvm::DIScope *RecordTy, const RecordDecl *RD) argument
1272 createFieldType(StringRef name, QualType type, SourceLocation loc, AccessSpecifier AS, uint64_t offsetInBits, uint32_t AlignInBits, llvm::DIFile *tunit, llvm::DIScope *scope, const RecordDecl *RD) argument
1338 CreateRecordStaticField(const VarDecl *Var, llvm::DIType *RecordTy, const RecordDecl *RD) argument
1367 CollectRecordNormalField( const FieldDecl *field, uint64_t OffsetInBits, llvm::DIFile *tunit, SmallVectorImpl<llvm::Metadata *> &elements, llvm::DIType *RecordTy, const RecordDecl *RD) argument
1483 const CXXRecordDecl *RD = ThisPtr->getPointeeCXXRecordDecl(); local
1525 isFunctionLocalClass(const CXXRecordDecl *RD) argument
1668 CollectCXXMemberFunctions( const CXXRecordDecl *RD, llvm::DIFile *Unit, SmallVectorImpl<llvm::Metadata *> &EltTys, llvm::DIType *RecordTy) argument
1706 CollectCXXBases(const CXXRecordDecl *RD, llvm::DIFile *Unit, SmallVectorImpl<llvm::Metadata *> &EltTys, llvm::DIType *RecordTy) argument
1721 CollectCXXBasesAux( const CXXRecordDecl *RD, llvm::DIFile *Unit, SmallVectorImpl<llvm::Metadata *> &EltTys, llvm::DIType *RecordTy, const CXXRecordDecl::base_class_const_range &Bases, llvm::DenseSet<CanonicalDeclPtr<const CXXRecordDecl>> &SeenTypes, llvm::DINode::DIFlags StartingFlags) argument
1938 getVTableName(const CXXRecordDecl *RD) argument
1995 CollectVTableInfo(const CXXRecordDecl *RD, llvm::DIFile *Unit, SmallVectorImpl<llvm::Metadata *> &EltTys, llvm::DICompositeType *RecordTy) argument
2101 completeType(const RecordDecl *RD) argument
2108 isClassOrMethodDLLImport(const CXXRecordDecl *RD) argument
2118 isDefinedInClangModule(const RecordDecl *RD) argument
2149 completeClassData(const RecordDecl *RD) argument
2163 completeClass(const RecordDecl *RD) argument
2186 shouldOmitDefinition(codegenoptions::DebugInfoKind DebugKind, bool DebugTypeExtRefs, const RecordDecl *RD, const LangOptions &LangOpts) argument
2243 completeRequiredType(const RecordDecl *RD) argument
2254 RecordDecl *RD = Ty->getDecl(); local
2267 RecordDecl *RD = Ty->getDecl(); local
3150 RecordDecl *RD = Ty->getDecl(); local
3233 CollectContainingType(const CXXRecordDecl *RD, llvm::DICompositeType *RealDecl) argument
4050 const RecordDecl *RD = RT->getDecl(); local
4420 CollectAnonRecordDecls( const RecordDecl *RD, llvm::DIFile *Unit, unsigned LineNo, StringRef LinkageName, llvm::GlobalVariable *Var, llvm::DIScope *DContext) argument
4484 const RecordDecl *RD = T->castAs<RecordType>()->getDecl(); local
4566 auto *RD = cast<RecordDecl>(VarD->getDeclContext()); local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcAsmPrinter.cpp115 MCOperand &Imm, MCOperand &RD,
120 SETHIInst.addOperand(RD);
126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD,
131 Inst.addOperand(RD);
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
140 EmitBinary(OutStreamer, SP::ORri, RS1, Imm, RD, STI);
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD,
146 EmitBinary(OutStreamer, SP::ADDrr, RS1, RS2, RD, STI);
150 MCOperand &RS1, MCOperand &Imm, MCOperand &RD,
152 EmitBinary(OutStreamer, SP::SLLri, RS1, Imm, RD, ST
114 EmitSETHI(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
125 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
137 EmitOR(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
143 EmitADD(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &RS2, MCOperand &RD, const MCSubtargetInfo &STI) argument
149 EmitSHL(MCStreamer &OutStreamer, MCOperand &RS1, MCOperand &Imm, MCOperand &RD, const MCSubtargetInfo &STI) argument
156 EmitHiLo(MCStreamer &OutStreamer, MCSymbol *GOTSym, SparcMCExpr::VariantKind HiKind, SparcMCExpr::VariantKind LoKind, MCOperand &RD, MCContext &OutContext, const MCSubtargetInfo &STI) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonBitSimplify.cpp228 static bool isTransparentCopy(const BitTracker::RegisterRef &RD,
922 // Check if RD could be replaced with RS at any possible use of RD.
926 bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD,
928 if (!Register::isVirtualRegister(RD.Reg) ||
932 auto *DRC = getFinalVRegClass(RD, MRI);
1066 bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
1275 // Calculates the used bits in RD ("defined register"), and checks if these
1276 // bits in RS ("used register") and RD are identical.
1277 bool RedundantInstrElimination::usedBitsEqual(BitTracker::RegisterRef RD,
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H A DBitTracker.cpp726 RegisterRef RD = MI.getOperand(0);
727 assert(RD.Sub == 0);
734 uint16_t W = getRegBitWidth(RD);
736 Res.insert(RegisterCell::ref(getCell(RS, Inputs)), mask(RD.Reg, SS));
737 Res.insert(RegisterCell::ref(getCell(RT, Inputs)), mask(RD.Reg, ST));
738 putCell(RD, Res, Outputs);
745 RegisterRef RD = MI.getOperand(0);
747 assert(RD.Sub == 0);
748 uint16_t WD = getRegBitWidth(RD);
755 putCell(RD, Re
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/freebsd-11-stable/contrib/llvm-project/clang/lib/Index/
H A DIndexingContext.cpp159 } else if (const auto *RD = dyn_cast<CXXRecordDecl>(D)) {
160 if (RD->getInstantiatedFromMemberClass())
161 TKind = RD->getTemplateSpecializationKind();
201 else if (const auto *RD = dyn_cast<CXXRecordDecl>(D->getDeclContext()))
202 return RD->getInstantiatedFromMemberClass();
214 } else if (const auto *RD = dyn_cast<CXXRecordDecl>(D)) {
215 return RD->getInstantiatedFromMemberClass();
281 } else if (auto RD = dyn_cast<RecordDecl>(Parent)) {
282 if (RD->isAnonymousStructOrUnion())
H A DIndexTypeSourceInfo.cpp188 CXXRecordDecl *RD = TD->getTemplatedDecl();
189 if (!RD->hasDefinition())
191 RD = RD->getDefinition();
193 std::vector<const NamedDecl *> Symbols = RD->lookupDependentName(
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/Interp/
H A DProgram.cpp207 Record *Program::getOrCreateRecord(const RecordDecl *RD) { argument
209 RD = RD->getDefinition();
210 if (!RD)
214 auto It = Records.find(RD);
236 if (auto *CD = dyn_cast<CXXRecordDecl>(RD)) {
268 for (const FieldDecl *FD : RD->fields()) {
290 Record *R = new (Allocator) Record(RD, std::move(Bases), std::move(Fields),
292 Records.insert({RD, R});
/freebsd-11-stable/contrib/llvm-project/clang/lib/Sema/
H A DSemaFixItUtils.cpp208 const CXXRecordDecl *RD = T->getAsCXXRecordDecl(); local
209 if (!RD || !RD->hasDefinition())
211 if (LangOpts.CPlusPlus11 && !RD->hasUserProvidedDefaultConstructor())
213 if (RD->isAggregate())
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/
H A DItaniumCXXABI.cpp216 bool isNearlyEmpty(const CXXRecordDecl *RD) const override {
219 if (!RD->isDynamicClass())
222 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
229 getCopyConstructorForExceptionObject(CXXRecordDecl *RD) override {
233 void addCopyConstructorForExceptionObject(CXXRecordDecl *RD,
H A DDeclCXX.cpp174 const CXXRecordDecl *RD = WorkList.pop_back_val(); local
175 for (const CXXBaseSpecifier &BaseSpec : RD->bases()) {
583 auto Visit = [&](const CXXRecordDecl *RD) -> bool {
584 RD = RD->getCanonicalDecl();
592 if (!RD->data().HasBasesWithFields) {
598 if (RD == Base)
606 if (Bases.count(RD))
611 if (M.insert(RD).second)
612 WorkList.push_back(RD);
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H A DCXXInheritance.cpp468 CXXRecordDecl *RD = TD->getTemplatedDecl();
469 if (!RD)
471 return findOrdinaryMember(RD, Path, Name);
593 void Collect(const CXXRecordDecl *RD, bool VirtualBase,
600 void FinalOverriderCollector::Collect(const CXXRecordDecl *RD,
607 = ++SubobjectCount[cast<CXXRecordDecl>(RD->getCanonicalDecl())];
609 for (const auto &Base : RD->bases()) {
657 for (auto *M : RD->methods()) {
771 AddIndirectPrimaryBases(const CXXRecordDecl *RD, ASTContext &Context,
774 const ASTRecordLayout &Layout = Context.getASTRecordLayout(RD);
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H A DJSONNodeDumper.cpp319 const auto *RD = local
322 llvm::json::Object Val{{"name", RD->getName()}};
330 #define FIELD2(Name, Flag) if (RD->Flag()) Ret[Name] = true
334 createDefaultConstructorDefinitionData(const CXXRecordDecl *RD) { argument
349 createCopyConstructorDefinitionData(const CXXRecordDecl *RD) { argument
360 if (!RD->needsOverloadResolutionForCopyConstructor())
367 createMoveConstructorDefinitionData(const CXXRecordDecl *RD) { argument
377 if (!RD->needsOverloadResolutionForMoveConstructor())
384 createCopyAssignmentDefinitionData(const CXXRecordDecl *RD) { argument
399 createMoveAssignmentDefinitionData(const CXXRecordDecl *RD) { argument
414 createDestructorDefinitionData(const CXXRecordDecl *RD) argument
431 createCXXRecordDefinitionData(const CXXRecordDecl *RD) argument
815 VisitRecordDecl(const RecordDecl *RD) argument
820 VisitCXXRecordDecl(const CXXRecordDecl *RD) argument
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H A DCXXABI.h49 virtual bool isNearlyEmpty(const CXXRecordDecl *RD) const = 0;
/freebsd-11-stable/contrib/binutils/include/opcode/
H A Dsparc.h208 #define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */ macro
217 #define RD_G0 RD (~0)
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/CodeGen/
H A DCodeGenABITypes.h64 const CXXRecordDecl *RD,
83 /// be a field in RD directly (i.e. not an inherited field).
85 const RecordDecl *RD, const FieldDecl *FD);
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/UninitializedObject/
H A DUninitializedObjectChecker.cpp120 /// Checks whether RD contains a field with a name or type name that matches
122 static bool shouldIgnoreRecord(const RecordDecl *RD, StringRef Pattern);
282 const RecordDecl *RD = R->getValueType()->getAsRecordDecl()->getDefinition(); local
284 if (!RD) {
290 shouldIgnoreRecord(RD, Opts.IgnoredRecordsWithFieldPattern)) {
298 for (const FieldDecl *I : RD->fields()) {
352 const auto *CXXRD = dyn_cast<CXXRecordDecl>(RD);
502 static bool shouldIgnoreRecord(const RecordDecl *RD, StringRef Pattern) { argument
505 for (const FieldDecl *FD : RD->fields()) {
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Frontend/
H A DMultiplexConsumer.h69 void AssignInheritanceModel(CXXRecordDecl *RD) override;
70 void HandleVTable(CXXRecordDecl *RD) override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DTargetTransformInfo.cpp898 bool hasSameData(ReductionData &RD) const {
899 return Kind == RD.Kind && Opcode == RD.Opcode;
941 Optional<ReductionData> RD = getReductionData(I); local
942 if (!RD)
945 ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
948 ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
973 if (NextLevelOpL && NextLevelOpL != RD->RHS)
975 else if (NextLevelOpR && NextLevelOpR != RD->LHS)
978 NextLevelOp = NextLevelOpL ? RD
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