Searched refs:Opcode (Results 176 - 200 of 497) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXGenericToNVVM.cpp256 unsigned Opcode = C->getOpcode(); local
257 switch (Opcode) {
300 if (Instruction::isBinaryOp(Opcode)) {
305 if (Instruction::isCast(Opcode)) {
H A DNVPTXTargetTransformInfo.h89 unsigned Opcode, Type *Ty,
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DSimpleSValBuilder.cpp38 SVal evalBinOpNN(ProgramStateRef state, BinaryOperator::Opcode op,
40 SVal evalBinOpLL(ProgramStateRef state, BinaryOperator::Opcode op,
42 SVal evalBinOpLN(ProgramStateRef state, BinaryOperator::Opcode op,
53 SVal MakeSymIntVal(const SymExpr *LHS, BinaryOperator::Opcode op,
218 BinaryOperator::Opcode op,
313 static bool isInRelation(BinaryOperator::Opcode Rel, SymbolRef Sym,
372 BinaryOperator::Opcode Op,
402 BinaryOperator::Opcode ResultOp;
438 static bool shouldRearrange(ProgramStateRef State, BinaryOperator::Opcode Op,
447 BinaryOperator::Opcode O
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DInstructionSimplify.h243 Value *SimplifyUnOp(unsigned Opcode, Value *Op, const SimplifyQuery &Q);
247 Value *SimplifyUnOp(unsigned Opcode, Value *Op, FastMathFlags FMF,
251 Value *SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS,
256 Value *SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp260 unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const {
262 unsigned SCIdx = TII->get(Opcode).getSchedClass();
339 TargetSchedModel::computeReciprocalThroughput(unsigned Opcode) const {
340 unsigned SchedClass = TII->get(Opcode).getSchedClass();
H A DMachineFrameInfo.cpp199 unsigned Opcode = MI.getOpcode(); local
200 if (Opcode == FrameSetupOpcode || Opcode == FrameDestroyOpcode) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp172 int X86TTIImpl::getArithmeticInstrCost(unsigned Opcode, Type *Ty, argument
182 int ISD = TLI->InstructionOpcodeToISD(Opcode);
880 Opcode, Ty->getScalarType(), Op1Info, Op2Info,
886 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info);
1273 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, argument
1275 int ISD = TLI->InstructionOpcodeToISD(Opcode);
1650 return BaseT::getCastInstrCost(Opcode, Dst, Src);
1700 return BaseT::getCastInstrCost(Opcode, Dst, Src, I);
1703 int X86TTIImpl::getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, argument
1710 int ISD = TLI->InstructionOpcodeToISD(Opcode);
2385 getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) argument
2436 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, const Instruction *I) argument
2480 getMaskedMemoryOpCost(unsigned Opcode, Type *SrcTy, unsigned Alignment, unsigned AddressSpace) argument
2561 getArithmeticReductionCost(unsigned Opcode, Type *ValTy, bool IsPairwise) argument
3036 getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty) argument
3184 getGSVectorCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, unsigned Alignment, unsigned AddressSpace) argument
3255 getGSScalarCost(unsigned Opcode, Type *SrcVTy, bool VariableMask, unsigned Alignment, unsigned AddressSpace) argument
3292 getGatherScatterOpCost(unsigned Opcode, Type *SrcVTy, Value *Ptr, bool VariableMask, unsigned Alignment) argument
3558 getInterleavedMemoryOpCostAVX2(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) argument
3674 getInterleavedMemoryOpCostAVX512(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) argument
3799 getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond, bool UseMaskForGaps) argument
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H A DX86InstrFMA3Info.cpp130 /// \p Opcode is included. If the given \p Opcode is not recognized as FMA3
132 const X86InstrFMA3Group *llvm::getFMA3Group(unsigned Opcode, uint64_t TSFlags) { argument
162 return Group.Opcodes[FormIndex] < Opcode;
164 assert(I != Table.end() && I->Opcodes[FormIndex] == Opcode &&
/freebsd-11-stable/sys/contrib/dev/acpica/components/executer/
H A Dexstore.c546 if (WalkState->Opcode != AML_COPY_OBJECT_OP)
574 if (WalkState->Opcode == AML_STORE_OP)
632 if ((WalkState->Opcode == AML_COPY_OBJECT_OP) ||
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb1InstrInfo.cpp149 unsigned Opcode = N->getMachineOpcode(); local
150 if (Opcode == ARM::tADCS || Opcode == ARM::tSBCS)
H A DARMISelDAGToDAG.cpp233 void SelectMVE_LongShift(SDNode *N, uint16_t Opcode, bool Immediate,
478 unsigned Opcode = MCID.getOpcode(); local
479 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
494 return TII->isFpMLxInstruction(Opcode);
789 unsigned Opcode = Op->getOpcode(); local
790 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
825 unsigned Opcode = Op->getOpcode(); local
826 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
845 unsigned Opcode local
924 unsigned Opcode = Op->getOpcode(); local
1326 unsigned Opcode = Op->getOpcode(); local
1378 unsigned Opcode = Op->getOpcode(); local
1530 unsigned Opcode = 0; local
1637 unsigned Opcode = 0; local
1680 unsigned Opcode = 0; local
2461 uint16_t Opcode; local
2488 SelectMVE_LongShift(SDNode *N, uint16_t Opcode, bool Immediate, bool HasSaturationOperand) argument
2526 uint16_t Opcode; local
2596 uint16_t Opcode = Opcodes[TySize]; local
2987 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS; local
2997 unsigned Opcode; local
4677 unsigned Opcode; local
4712 unsigned Opcode = StringSwitch<unsigned>(SpecialReg) local
4792 unsigned Opcode; local
4827 unsigned Opcode = StringSwitch<unsigned>(SpecialReg) local
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H A DMLxExpansionPass.cpp188 unsigned Opcode = MCID.getOpcode(); local
189 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
196 static bool isFpMulInstruction(unsigned Opcode) { argument
197 switch (Opcode) {
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInst.h159 unsigned Opcode = 0; member in class:llvm::MCInst
171 void setOpcode(unsigned Op) { Opcode = Op; }
172 unsigned getOpcode() const { return Opcode; }
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DCorrelatedValuePropagation.cpp445 static void setDeducedOverflowingFlags(Value *V, Instruction::BinaryOps Opcode, argument
448 switch (Opcode) {
497 Instruction::BinaryOps Opcode = WO->getBinaryOp(); local
502 B.CreateBinOp(Opcode, WO->getLHS(), WO->getRHS(), WO->getName());
503 setDeducedOverflowingFlags(NewOp, Opcode, NSW, NUW);
520 Instruction::BinaryOps Opcode = SI->getBinaryOp(); local
524 Opcode, SI->getLHS(), SI->getRHS(), SI->getName(), SI);
526 setDeducedOverflowingFlags(BinOp, Opcode, NSW, NUW);
757 Instruction::BinaryOps Opcode = BinOp->getOpcode(); local
768 Opcode, RRang
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp73 unsigned Opcode = 0; local
85 Opcode = IsValidInc ? Hexagon::L2_loadrub_pi : Hexagon::L2_loadrub_io;
87 Opcode = IsValidInc ? Hexagon::L2_loadrb_pi : Hexagon::L2_loadrb_io;
91 Opcode = IsValidInc ? Hexagon::L2_loadruh_pi : Hexagon::L2_loadruh_io;
93 Opcode = IsValidInc ? Hexagon::L2_loadrh_pi : Hexagon::L2_loadrh_io;
99 Opcode = IsValidInc ? Hexagon::L2_loadri_pi : Hexagon::L2_loadri_io;
106 Opcode = IsValidInc ? Hexagon::L2_loadrd_pi : Hexagon::L2_loadrd_io;
118 Opcode = IsValidInc ? Hexagon::V6_vL32b_nt_pi : Hexagon::V6_vL32b_nt_ai;
120 Opcode = IsValidInc ? Hexagon::V6_vL32b_pi : Hexagon::V6_vL32b_ai;
122 Opcode
475 unsigned Opcode = 0; local
1671 unsigned Opcode; member in class:__anon2252::LeafPrioQueue
1731 LeafPrioQueue(unsigned Opcode) argument
2268 unsigned Opcode = N->getOpcode(); local
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H A DHexagonInstrInfo.cpp2158 bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
2159 return (Opcode == Hexagon::ENDLOOP0 ||
2160 Opcode == Hexagon::ENDLOOP1);
2213 unsigned Opcode = MI.getOpcode(); local
2214 const uint64_t F = get(Opcode).TSFlags;
2357 unsigned Opcode = MI.getOpcode(); local
2358 return Opcode == Hexagon::J2_loop0i ||
2359 Opcode == Hexagon::J2_loop0r ||
2360 Opcode == Hexagon::J2_loop0iext ||
2361 Opcode
2676 isValidOffset(unsigned Opcode, int Offset, const TargetRegisterInfo *TRI, bool Extend) const argument
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/
H A DPatternMatch.h757 template <typename LHS_t, typename RHS_t, unsigned Opcode,
768 if (V->getValueID() == Value::InstructionVal + Opcode) {
775 return CE->getOpcode() == Opcode &&
934 template <typename LHS_t, typename RHS_t, unsigned Opcode,
945 if (Op->getOpcode() != Opcode)
1047 bool isOpType(unsigned Opcode) { return Instruction::isShift(Opcode); } argument
1051 bool isOpType(unsigned Opcode) { argument
1052 return Opcode == Instruction::LShr || Opcode
1057 isOpType(unsigned Opcode) argument
1063 isOpType(unsigned Opcode) argument
1069 isOpType(unsigned Opcode) argument
1075 isOpType(unsigned Opcode) argument
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/freebsd-11-stable/sys/contrib/dev/acpica/include/
H A Dacinterp.h178 UINT8 Opcode; member in struct:acpi_exdump_info
184 /* Values for the Opcode field above */
377 UINT16 Opcode,
384 UINT16 Opcode,
391 UINT16 Opcode,
629 UINT16 Opcode,
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DPredicateExpander.cpp231 for (const Record *Opcode : Opcodes) {
233 OS << "case " << Opcode->getValueAsString("Namespace")
234 << "::" << Opcode->getName() << ":\n";
482 for (const Record *Opcode : Group.getOpcodes()) {
485 OS << "case " << getTargetName() << "::" << Opcode->getName() << ":";
H A DFastISelEmitter.cpp705 const std::string &Opcode = I->first;
708 OS << "// FastEmit functions for " << Opcode << ".\n";
723 << getLegalCName(Opcode)
736 << getLegalCName(Opcode) << "_"
748 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT))
760 << getLegalCName(Opcode) << "_"
780 << getLegalCName(Opcode) << "_";
793 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_";
814 OS << "(MVT VT, MVT RetVT, unsigned Opcode";
843 OS << "(VT, RetVT, Opcode";
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp294 int Opcode = SU->getInstr()->getOpcode(); local
296 if (TII->usesTextureCache(Opcode) || TII->usesVertexCache(Opcode))
299 if (TII->isALUInstr(Opcode)) {
303 switch (Opcode) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp270 unsigned Opcode = candidate->getOpcode(); local
275 Opcode >= SP::LDDArr && Opcode <= SP::LDrr)
281 Opcode >= SP::FDIVD && Opcode <= SP::FSQRTD)
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp546 unsigned Opcode; local
548 Opcode = Mips::TRUNC_W_S;
550 Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32;
552 MachineInstr *Trunc = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Opcode))
644 unsigned Opcode; member in struct:Instr
646 Instr(unsigned Opcode, Register Def, Register LHS, Register RHS) argument
647 : Opcode(Opcode), Def(Def), LHS(LHS), RHS(RHS){};
650 if (Opcode == Mips::SLTiu || Opcode
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H A DMipsDelaySlotFiller.cpp578 static int getEquivalentCallShort(int Opcode) { argument
579 switch (Opcode) {
744 unsigned Opcode = (*Slot).getOpcode(); local
751 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
752 Opcode == Mips::PseudoIndirectBranch_MM ||
753 Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL))
757 if (InMicroMipsMode && (Opcode == Mips::LWP_MM || Opcode
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Analysis/
H A DInstructionSimplify.cpp232 /// "(A op B) op' (A op C)". Here "op" is given by Opcode and "op'" is
236 static Value *ExpandBinOp(Instruction::BinaryOps Opcode, Value *LHS, Value *RHS, argument
249 if (Value *L = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse))
250 if (Value *R = SimplifyBinOp(Opcode, B, C, Q, MaxRecurse)) {
272 if (Value *L = SimplifyBinOp(Opcode, A, B, Q, MaxRecurse))
273 if (Value *R = SimplifyBinOp(Opcode, A, C, Q, MaxRecurse)) {
294 static Value *SimplifyAssociativeBinOp(Instruction::BinaryOps Opcode, argument
298 assert(Instruction::isAssociative(Opcode) && "Not an associative operation!");
308 if (Op0 && Op0->getOpcode() == Opcode) {
314 if (Value *V = SimplifyBinOp(Opcode,
394 ThreadBinOpOverSelect(Instruction::BinaryOps Opcode, Value *LHS, Value *RHS, const SimplifyQuery &Q, unsigned MaxRecurse) argument
518 ThreadBinOpOverPHI(Instruction::BinaryOps Opcode, Value *LHS, Value *RHS, const SimplifyQuery &Q, unsigned MaxRecurse) argument
601 foldOrCommuteConstant(Instruction::BinaryOps Opcode, Value *&Op0, Value *&Op1, const SimplifyQuery &Q) argument
1049 simplifyDiv(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument
1107 simplifyRem(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument
1236 SimplifyShift(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, const SimplifyQuery &Q, unsigned MaxRecurse) argument
1286 SimplifyRightShift(Instruction::BinaryOps Opcode, Value *Op0, Value *Op1, bool isExact, const SimplifyQuery &Q, unsigned MaxRecurse) argument
4525 foldConstant(Instruction::UnaryOps Opcode, Value *&Op, const SimplifyQuery &Q) argument
4811 simplifyUnOp(unsigned Opcode, Value *Op, const SimplifyQuery &Q, unsigned MaxRecurse) argument
4824 simplifyFPUnOp(unsigned Opcode, Value *Op, const FastMathFlags &FMF, const SimplifyQuery &Q, unsigned MaxRecurse) argument
4835 SimplifyUnOp(unsigned Opcode, Value *Op, const SimplifyQuery &Q) argument
4839 SimplifyUnOp(unsigned Opcode, Value *Op, FastMathFlags FMF, const SimplifyQuery &Q) argument
4846 SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, const SimplifyQuery &Q, unsigned MaxRecurse) argument
4893 SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, const FastMathFlags &FMF, const SimplifyQuery &Q, unsigned MaxRecurse) argument
4910 SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, const SimplifyQuery &Q) argument
4915 SimplifyBinOp(unsigned Opcode, Value *LHS, Value *RHS, FastMathFlags FMF, const SimplifyQuery &Q) argument
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