Searched refs:Opcode (Results 126 - 150 of 497) sorted by relevance

1234567891011>>

/freebsd-11-stable/sys/contrib/dev/acpica/compiler/
H A Ddtsubtable.c407 if (Info->Opcode == ACPI_DMT_EXTRA_TEXT)
419 switch (Info->Opcode)
H A Dcvparser.c715 UINT16 Opcode = (UINT16) ACPI_GET8 (Aml); local
724 Opcode != AML_COMMENT_OP)
729 while (Opcode == AML_COMMENT_OP)
932 /* Peek at the next Opcode. */
935 Opcode = (UINT16) ACPI_GET8 (Aml);
972 UINT16 Opcode; local
986 Opcode = (UINT16) ACPI_GET8 (Aml);
987 OpInfo = AcpiPsGetOpcodeInfo (Opcode);
/freebsd-11-stable/sys/contrib/dev/acpica/components/parser/
H A Dpsparse.c177 * PARAMETERS: Opcode - An AML opcode
187 UINT32 Opcode)
192 if (Opcode > 0x00FF)
220 UINT16 Opcode; local
224 Opcode = (UINT16) ACPI_GET8 (Aml);
226 if (Opcode == AML_EXTENDED_PREFIX)
231 Opcode = (UINT16) ((Opcode << 8) | ACPI_GET8 (Aml));
234 return (Opcode);
186 AcpiPsGetOpcodeSize( UINT32 Opcode) argument
/freebsd-11-stable/contrib/llvm-project/clang/include/clang/StaticAnalyzer/Core/PathSensitive/
H A DSValBuilder.h117 virtual SVal evalBinOpNN(ProgramStateRef state, BinaryOperator::Opcode op,
122 virtual SVal evalBinOpLL(ProgramStateRef state, BinaryOperator::Opcode op,
128 virtual SVal evalBinOpLN(ProgramStateRef state, BinaryOperator::Opcode op,
141 SVal makeSymExprValNN(BinaryOperator::Opcode op,
144 SVal evalBinOp(ProgramStateRef state, BinaryOperator::Opcode op,
322 NonLoc makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
325 NonLoc makeNonLoc(const llvm::APSInt& rhs, BinaryOperator::Opcode op,
328 NonLoc makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstPrinter.h87 StringRef getOpcodeName(unsigned Opcode) const;
116 uint32_t Opcode; member in struct:llvm::PatternsForOpcode
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp124 const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const {
125 switch ((VEISD::NodeType)Opcode) {
H A DVEISelLowering.h36 const char *getTargetNodeName(unsigned Opcode) const override;
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreFrameLowering.cpp106 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; local
107 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
128 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; local
129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
201 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; local
202 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
262 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; local
264 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
287 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; local
289 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
400 int Opcode = isImmU6(RemainingAdj) ? XCore::RETSP_u6 : XCore::RETSP_lu6; local
407 int Opcode = isImmU6(RemainingAdj) ? XCore::LDAWSP_ru6 : local
517 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; local
521 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp143 unsigned Opcode = 0; local
145 Opcode = AVR::STDPtrQRr;
147 Opcode = AVR::STDWPtrQRr;
152 BuildMI(MBB, MI, DL, get(Opcode))
177 unsigned Opcode = 0; local
179 Opcode = AVR::LDDRdPtrQ;
181 // Opcode = AVR::LDDWRdPtrQ;
183 Opcode = AVR::LDDWRdYQ;
188 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
477 unsigned Opcode local
[all...]
H A DAVRISelDAGToDAG.cpp134 unsigned Opcode = 0; local
144 Opcode = (isPre) ? AVR::LDRdPtrPd : AVR::LDRdPtrPi;
152 Opcode = (isPre) ? AVR::LDWRdPtrPd : AVR::LDWRdPtrPi;
159 SDNode *ResNode = CurDAG->getMachineNode(Opcode, SDLoc(N), VT,
177 unsigned Opcode = 0; local
185 Opcode = AVR::LPMRdZPi;
192 Opcode = AVR::LPMWRdZPi;
199 return Opcode;
533 unsigned Opcode = N->getOpcode(); local
536 switch (Opcode) {
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNHazardRecognizer.cpp61 static bool isDivFMas(unsigned Opcode) { argument
62 return Opcode == AMDGPU::V_DIV_FMAS_F32 || Opcode == AMDGPU::V_DIV_FMAS_F64;
65 static bool isSGetReg(unsigned Opcode) { argument
66 return Opcode == AMDGPU::S_GETREG_B32;
69 static bool isSSetReg(unsigned Opcode) { argument
70 return Opcode == AMDGPU::S_SETREG_B32 || Opcode == AMDGPU::S_SETREG_IMM32_B32;
73 static bool isRWLane(unsigned Opcode) { argument
74 return Opcode
77 isRFE(unsigned Opcode) argument
81 isSMovRel(unsigned Opcode) argument
120 unsigned Opcode = MI.getOpcode(); local
674 unsigned Opcode = MI.getOpcode(); local
[all...]
H A DAMDGPUMCInstLower.cpp177 unsigned Opcode = MI->getOpcode(); local
183 if (Opcode == AMDGPU::S_SETPC_B64_return)
184 Opcode = AMDGPU::S_SETPC_B64;
185 else if (Opcode == AMDGPU::SI_CALL) {
195 } else if (Opcode == AMDGPU::SI_TCRETURN) {
197 Opcode = AMDGPU::S_SETPC_B64;
200 int MCOpcode = TII->pseudoToMCOpcode(Opcode);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DReassociate.cpp148 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) { argument
150 if (I && I->hasOneUse() && I->getOpcode() == Opcode)
304 static void IncorporateWeight(APInt &LHS, const APInt &RHS, unsigned Opcode) { argument
322 if (Instruction::isIdempotent(Opcode)) {
329 if (Instruction::isNilpotent(Opcode)) {
335 if (Opcode == Instruction::Add || Opcode == Instruction::FAdd) {
341 assert((Opcode == Instruction::Mul || Opcode == Instruction::FMul) &&
458 unsigned Opcode local
651 unsigned Opcode = I->getOpcode(); local
1132 OptimizeAndOrXor(unsigned Opcode, SmallVectorImpl<ValueEntry> &Ops) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h90 PPCII::PPC970_Unit GetInstrType(unsigned Opcode,
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/
H A DRangedConstraintManager.cpp34 BinaryOperator::Opcode op = SIE->getOpcode();
50 BinaryOperator::Opcode Op = SSE->getOpcode();
121 BinaryOperator::Opcode Op,
188 BinaryOperator::Opcode Op = SE->getOpcode();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsNaClELFStreamer.cpp74 unsigned Opcode = MI.getOpcode(); local
78 switch (Opcode) {
210 bool isBasePlusOffsetMemoryAccess(unsigned Opcode, unsigned *AddrIdx, argument
215 switch (Opcode) {
/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/xray/
H A Dxray_mips64.cpp41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs,
44 return (Opcode | Rs << 21 | Rt << 16 | Imm);
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd,
50 return (Rs << 21 | Rt << 16 | Rd << 11 | Imm << 6 | Opcode);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSERegisterInfo.cpp65 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode, argument
67 switch (Opcode) {
129 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) { argument
130 switch (Opcode) {
H A DMipsExpandPseudo.cpp346 unsigned Opcode = 0; local
364 Opcode = Mips::ADDu;
370 Opcode = Mips::SUBu;
376 Opcode = Mips::AND;
382 Opcode = Mips::OR;
388 Opcode = Mips::XOR;
516 BuildMI(loopMBB, DL, TII->get(Opcode), BinOpRes)
637 unsigned Opcode = 0; local
649 Opcode = Mips::ADDu;
652 Opcode
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.h32 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIndex);
/freebsd-11-stable/contrib/llvm-project/clang/lib/AST/Interp/
H A DDisasm.cpp14 #include "Opcode.h"
50 auto Op = PC.read<Opcode>();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp94 unsigned Opcode = MI.getOpcode(); local
120 switch (Opcode) {
273 Opcode == TargetOpcode::G_FCMP) ==
326 switch (Opcode) {
380 unsigned Opcode = MI.getOpcode(); local
382 if (Opcode == TargetOpcode::G_CONSTANT)
400 switch (Opcode) {
/freebsd-11-stable/sys/contrib/dev/acpica/components/dispatcher/
H A Ddswload2.c212 (WalkState->Opcode != AML_INT_NAMEPATH_OP)) ||
220 if (WalkState->Opcode == AML_INT_NAMEPATH_OP)
253 switch (WalkState->Opcode)
445 if (WalkState->Opcode == AML_EXTERNAL_OP)
476 Op = AcpiPsAllocOp (WalkState->Opcode, WalkState->Aml);
532 ACPI_DEBUG_PRINT ((ACPI_DB_DISPATCH, "Opcode [%s] Op %p State %p\n",
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFMIPeephole.cpp307 unsigned Opcode = MI.getOpcode(); local
308 if (Opcode == BPF::MOV_32_64 ||
309 Opcode == BPF::MOV_rr || Opcode == BPF::MOV_rr_32) {
313 if (Opcode == BPF::MOV_32_64)
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DTargetTransformInfoImpl.h47 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) { argument
48 switch (Opcode) {
355 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm, argument
362 unsigned getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, argument
432 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty, argument
447 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, argument
450 unsigned getExtractWithExtendCost(unsigned Opcode, Type *Dst, argument
455 unsigned getCFInstrCost(unsigned Opcode) { return 1; } argument
457 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, argument
462 unsigned getVectorInstrCost(unsigned Opcode, Typ argument
466 getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, unsigned AddressSpace, const Instruction *I) argument
471 getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment, unsigned AddressSpace) argument
476 getGatherScatterOpCost(unsigned Opcode, Type *DataTy, Value *Ptr, bool VariableMask, unsigned Alignment) argument
482 getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond = false, bool UseMaskForGaps = false) argument
606 useReductionIntrinsic(unsigned Opcode, Type *Ty, TTI::ReductionFlags Flags) const argument
[all...]

Completed in 162 milliseconds

1234567891011>>