/freebsd-11-stable/contrib/llvm-project/compiler-rt/lib/scudo/standalone/ |
H A D | internal_defs.h | 84 #define CHECK_IMPL(C1, Op, C2) \ 88 if (UNLIKELY(!(V1 Op V2))) { \ 90 "(" #C1 ") " #Op " (" #C2 ")", V1, V2); \
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/ |
H A D | RISCVISelLowering.cpp | 175 for (auto Op : FPOpToExtend) 176 setOperationAction(Op, MVT::f32, Expand); 194 for (auto Op : FPOpToExtend) 195 setOperationAction(Op, MVT::f64, Expand); 391 SDValue RISCVTargetLowering::LowerOperation(SDValue Op, argument 393 switch (Op.getOpcode()) { 397 return lowerGlobalAddress(Op, DAG); 399 return lowerBlockAddress(Op, DAG); 401 return lowerConstantPool(Op, DAG); 403 return lowerGlobalTLSAddress(Op, DA 490 lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const argument 512 lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const argument 519 lowerConstantPool(SDValue Op, SelectionDAG &DAG) const argument 599 lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const argument 633 lowerSELECT(SDValue Op, SelectionDAG &DAG) const argument 673 lowerVASTART(SDValue Op, SelectionDAG &DAG) const argument 688 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const argument 711 lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const argument 741 lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const argument 780 lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const argument 1114 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument 2725 LowerAsmOperandForConstraint( SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops, SelectionDAG &DAG) const argument [all...] |
H A D | RISCVISelDAGToDAG.cpp | 49 bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, 174 const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) { 179 OutOps.push_back(Op); 182 OutOps.push_back(Op); 173 SelectInlineAsmMemoryOperand( const SDValue &Op, unsigned ConstraintID, std::vector<SDValue> &OutOps) argument
|
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/IR/ |
H A D | InstrTypes.h | 61 : Instruction(Ty, iType, &Op<0>(), 1, IB) { 62 Op<0>() = V; 65 : Instruction(Ty, iType, &Op<0>(), 1, IAE) { 66 Op<0>() = V; 124 static UnaryOperator *Create(UnaryOps Op, Value *S, 132 static UnaryOperator *Create(UnaryOps Op, Value *S, 166 static UnaryOperator *CreateFNegFMF(Value *Op, Instruction *FMFSource, argument 168 return CreateWithCopiedFlags(Instruction::FNeg, Op, FMFSource, Name); 216 static BinaryOperator *Create(BinaryOps Op, Value *S1, Value *S2, 224 static BinaryOperator *Create(BinaryOps Op, Valu 283 CreateFNegFMF(Value *Op, Instruction *FMFSource, const Twine &Name = �) argument [all...] |
/freebsd-11-stable/contrib/llvm-project/clang/lib/StaticAnalyzer/Core/ |
H A D | SVals.cpp | 243 BinaryOperator::Opcode Op, 246 svalBuilder.getBasicValueFactory().evalAPSInt(Op, getValue(), R.getValue()); 269 BinaryOperator::Opcode Op, 271 assert(BinaryOperator::isComparisonOp(Op) || Op == BO_Sub); 273 const llvm::APSInt *X = BasicVals.evalAPSInt(Op, getValue(), R.getValue()); 242 evalBinOp(SValBuilder &svalBuilder, BinaryOperator::Opcode Op, const nonloc::ConcreteInt& R) const argument 268 evalBinOp(BasicValueFactory& BasicVals, BinaryOperator::Opcode Op, const loc::ConcreteInt& R) const argument
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/ObjCARC/ |
H A D | ObjCARCAPElim.cpp | 159 Value *Op = *OI; local 162 Function *F = dyn_cast<Function>(cast<ConstantStruct>(Op)->getOperand(1));
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/ |
H A D | X86FloatingPoint.cpp | 983 MachineOperand &Op = MI.getOperand(i); local 984 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) 987 assert(Op.isImplicit() && "Expected implicit def/use"); 989 if (Op.isDef()) 990 STReturns |= 1 << getFPReg(Op); 1024 MachineOperand &Op = MI.getOperand(i); local 1025 if (!Op.isReg() || Op 1609 MachineOperand &Op = MI.getOperand(i); local 1638 MachineOperand &Op = MI.getOperand(i); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | AsmMatcherEmitter.cpp | 588 auto I = find_if(AsmOperands, [&](const AsmOperand &Op) { 589 return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx; 598 [&](const AsmOperand &Op) { return Op.SrcOpName == N; }); 605 [&](const AsmOperand &Op) { return Op.OrigSrcOpName == N; }); 765 MatchableInfo::AsmOperand &Op); 807 const AsmOperand &Op = AsmOperands[i]; 808 errs() << " op[" << i << "] = " << Op [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64SpeculationHardening.cpp | 484 bool AllDefsAreGPR = llvm::all_of(MI.defs(), [&](MachineOperand &Op) { 485 return Op.isReg() && (AArch64::GPR32allRegClass.contains(Op.getReg()) || 486 AArch64::GPR64allRegClass.contains(Op.getReg())); 498 for (MachineOperand Op : MI.defs()) 499 for (MCRegAliasIterator AI(Op.getReg(), TRI, true); AI.isValid(); ++AI) 570 for (MachineOperand Op : MI.defs()) 571 for (MCRegAliasIterator AI(Op.getReg(), TRI, true); AI.isValid(); ++AI) 631 for (MachineOperand Op : MI.uses()) 632 if (Op [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonLoopIdiomRecognition.cpp | 281 for (Value *Op : U->operands()) 282 Q.push_back(Op); 304 for (const Value *Op : U->operands()) { 306 print(OS, Op); 328 for (Value *Op : U->operands()) 329 Q.push_back(Op); 394 Value *Op = U->getOperand(i); local 395 if (Op == OldV) { 399 Q.push_back(Op); 430 for (Value *Op 1031 Value *Op = Z->getOperand(0); local 1287 isOperandShifted(Instruction *I, Value *Op) argument 1408 Value *Op = J.get(); local [all...] |
H A D | RDFCopy.cpp | 170 MachineOperand &Op = UA.Addr->getOp(); local 171 if (Op.isTied()) 180 Op.setReg(NewReg); 181 Op.setSubReg(0);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIFoldOperands.cpp | 444 auto &Op = MI->getOperand(i); local 446 TII->isLiteralConstantLike(Op, OpInfo)) { 486 MachineOperand *Op = &SubDef->getOperand(1); local 487 if (Op->isImm()) { 488 if (TII->isInlineConstant(*Op, OpTy)) 489 Sub = Op; 492 if (!Op->isReg()) 494 Sub = Op; 542 const MachineOperand *Op = Defs[I].first; local 543 if (!Op 965 getImmOrMaterializedImm(MachineRegisterInfo &MRI, MachineOperand &Op) argument 1264 unsigned Op = MI.getOpcode(); local 1379 unsigned Op = MI.getOpcode(); local [all...] |
H A D | SIPeepholeSDWA.cpp | 81 Optional<int64_t> foldToImm(const MachineOperand &Op) const; 518 Optional<int64_t> SIPeepholeSDWA::foldToImm(const MachineOperand &Op) const { 519 if (Op.isImm()) { 520 return Op.getImm(); 525 if (Op.isReg()) { 526 for (const MachineOperand &Def : MRI->def_operands(Op.getReg())) { 527 if (!isSameReg(Op, Def)) 1180 for (MachineOperand &Op : MI.explicit_uses()) { 1181 if (!Op.isImm() && !(Op [all...] |
H A D | R600ExpandSpecialInstrs.cpp | 44 unsigned Op); 74 const MachineInstr *OldMI, unsigned Op) { 75 int OpIdx = TII->getOperandIdx(*OldMI, Op); 78 TII->setImmOperand(*NewMI, Op, Val); 73 SetFlagInNewMI(MachineInstr *NewMI, const MachineInstr *OldMI, unsigned Op) argument
|
H A D | SIFixupVectorISel.cpp | 85 static bool findSRegBaseAndIndex(MachineOperand *Op, argument 91 Worklist.push_back(Op); 177 MachineOperand *Op = TII->getNamedOperand(MI, AMDGPU::OpName::vaddr); local 178 if (!findSRegBaseAndIndex(Op, BaseReg, IndexReg, MRI, TRI))
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/ |
H A D | RISCVAsmParser.cpp | 65 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 302 // modifiers and isShiftedInt<N-1, 1>(Op). 660 auto Op = std::make_unique<RISCVOperand>(KindTy::Token); local 661 Op->Tok = Str; 662 Op->StartLoc = S; 663 Op->EndLoc = S; 664 Op->IsRV64 = IsRV64; 665 return Op; 670 auto Op = std::make_unique<RISCVOperand>(KindTy::Register); local 671 Op 680 auto Op = std::make_unique<RISCVOperand>(KindTy::Immediate); local 690 auto Op = std::make_unique<RISCVOperand>(KindTy::SystemRegister); local 777 RISCVOperand &Op = static_cast<RISCVOperand &>(AsmOp); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 772 /// Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all 773 /// elements. VT must be a vector type. Op's type must be the same as (or, 775 SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op) { argument 777 if (Op.getOpcode() == ISD::UNDEF) { 778 assert((VT.getVectorElementType() == Op.getValueType() || 780 VT.getVectorElementType().bitsLE(Op.getValueType()))) && 786 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Op); 790 // Return a splat ISD::SPLAT_VECTOR node, consisting of Op splatted to all 792 SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op) { argument 793 if (Op 1594 isKnownNeverSNaN(SDValue Op, unsigned Depth = 0) const argument [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/FuzzMutate/ |
H A D | IRMutator.cpp | 97 auto OpMatchesPred = [&Src](fuzzerop::OpDescriptor &Op) { 98 return Op.SourcePreds[0].matches({}, Src); 133 if (Value *Op = OpDesc->BuilderFunc(Srcs, Insts[IP])) { 135 IB.connectToSink(BB, InstsAfter, Op);
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64WinCOFFStreamer.cpp | 80 unsigned Op = Win64EH::UOP_AllocSmall; local 82 Op = Win64EH::UOP_AllocLarge; 84 Op = Win64EH::UOP_AllocMedium; 85 EmitARM64WinUnwindCode(Op, -1, Size);
|
/freebsd-11-stable/contrib/llvm-project/clang/lib/Analysis/ |
H A D | ThreadSafetyTIL.cpp | 19 StringRef til::getUnaryOpcodeString(TIL_UnaryOpcode Op) { argument 20 switch (Op) { 28 StringRef til::getBinaryOpcodeString(TIL_BinaryOpcode Op) { argument 29 switch (Op) {
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
H A D | VPlanHCFGBuilder.cpp | 102 for (Value *Op : Phi->operands()) 103 VPPhi->addOperand(getOrCreateVPOperand(Op)); 225 for (Value *Op : Inst->operands()) 226 VPOperands.push_back(getOrCreateVPOperand(Op));
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86ATTInstPrinter.h | 42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS); 44 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O); 45 void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O); 46 void printU8Imm(const MCInst *MI, unsigned Op, raw_ostream &OS);
|
H A D | X86WinCOFFTargetStreamer.cpp | 52 } Op; member in struct:__anon2474::FPOInstruction 208 Inst.Op = FPOInstruction::SetFrame; 219 Inst.Op = FPOInstruction::PushReg; 230 Inst.Op = FPOInstruction::StackAlloc; 240 return Inst.Op == FPOInstruction::SetFrame; 248 Inst.Op = FPOInstruction::StackAlign; 415 switch (Inst.Op) {
|
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 210 SDValue Op = DisintegrateMERGE_VALUES(N, ResNo); local 211 return GetPromotedInteger(Op); 216 SDValue Op = SExtPromotedInteger(N->getOperand(0)); local 218 Op.getValueType(), Op, N->getOperand(1)); 223 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); local 225 Op.getValueType(), Op, N->getOperand(1)); 412 SDValue Op = GetPromotedInteger(N->getOperand(0)); 414 EVT NVT = Op 424 SDValue Op = GetPromotedInteger(N->getOperand(0)); local 461 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); local 475 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); local 480 SDValue Op = GetPromotedInteger(N->getOperand(0)); local 965 SDValue Op = GetPromotedInteger(N->getOperand(0)); local 1409 SDValue Op = GetPromotedInteger(N->getOperand(0)); local 1572 SDValue Op = GetPromotedInteger(N->getOperand(0)); local 1679 SDValue Op = GetPromotedInteger(N->getOperand(0)); local 1695 SDValue Op = GetPromotedInteger(N->getOperand(0)); local 1722 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); local 1739 SDValue Op = SExtPromotedInteger(N->getOperand(1)); local 1745 SDValue Op; local 2216 getExpandedMinMaxOps(int Op) argument 2519 SDValue Op = N->getOperand(0); local 2700 SDValue Op = N->getOperand(IsStrict ? 1 : 0); local 2723 SDValue Op = N->getOperand(IsStrict ? 1 : 0); local 2740 SDValue Op = N->getOperand(N->isStrictFPOpcode() ? 1 : 0); local 3432 SDValue Op = N->getOperand(0); local 3701 SDValue Op = N->getOperand(0); local 4053 SDValue Op = N->getOperand(IsStrict ? 1 : 0); local 4173 SDValue Op = N->getOperand(IsStrict ? 1 : 0); local 4229 SDValue Op = DAG.getAnyExtOrTrunc(Ext, dl, NOutVTElem); local 4265 SDValue Op; local 4292 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(0)); local 4309 SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutElemVT, SplatVal); local 4332 SDValue Op = N->getOperand(i); local [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
H A D | SIMCCodeEmitter.cpp | 314 // Check for additional literals in SRC0/1/2 (Op 1/2/3) 322 const MCOperand &Op = MI.getOperand(i); local 323 if (getLitEncoding(Op, Desc.OpInfo[i], STI) != 255) 329 if (Op.isImm()) 330 Imm = Op.getImm(); 331 else if (Op.isExpr()) { 332 if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr())) 335 } else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
|