Searched refs:MRI (Results 26 - 50 of 513) sorted by relevance

1234567891011>>

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUMacroFusion.cpp45 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); local
46 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
H A DAMDGPUGlobalISelUtils.cpp17 AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) { argument
18 MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
36 if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
40 if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
H A DSIRegisterInfo.h138 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const { argument
141 RC = MRI.getRegClass(Reg);
199 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
207 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
209 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
210 bool isAGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
211 bool isVectorRegister(const MachineRegisterInfo &MRI, unsigned Reg) const { argument
212 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
257 const MachineRegisterInfo &MRI) cons
[all...]
H A DSIFixupVectorISel.cpp88 MachineRegisterInfo &MRI,
96 MachineInstr *DefInst = MRI.getUniqueVRegDef(WOp->getReg());
120 MachineInstr *MI = MRI.getUniqueVRegDef(IndexReg);
127 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg());
132 MI = MRI.getUniqueVRegDef(BaseReg);
137 BaseRC = MRI.getRegClass(BaseReg);
141 if (!TRI->isSGPRReg(MRI, BaseReg))
143 if (!TRI->hasVGPRs(MRI.getRegClass(IndexReg)))
146 MRI.clearKillFlags(IndexReg);
147 MRI
85 findSRegBaseAndIndex(MachineOperand *Op, unsigned &BaseReg, unsigned &IndexReg, MachineRegisterInfo &MRI, const SIRegisterInfo *TRI) argument
155 fixupGlobalSaddr(MachineBasicBlock &MBB, MachineFunction &MF, MachineRegisterInfo &MRI, const GCNSubtarget &ST, const SIInstrInfo *TII, const SIRegisterInfo *TRI) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXPeephole.cpp82 const auto &MRI = MF.getRegInfo(); local
85 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
107 const auto &MRI = MF.getRegInfo(); local
109 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
119 // Check if MRI has only one non dbg use, which is Root
120 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
146 const auto &MRI = MF.getRegInfo(); local
147 if (MRI.use_empty(NVPTX::VRFrame)) {
148 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstructionSelector.cpp80 bool earlySelectSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
84 MachineRegisterInfo &MRI) const;
87 MachineRegisterInfo &MRI) const;
89 MachineRegisterInfo &MRI) const;
92 MachineRegisterInfo &MRI) const;
94 bool selectVectorASHR(MachineInstr &I, MachineRegisterInfo &MRI) const;
95 bool selectVectorSHL(MachineInstr &I, MachineRegisterInfo &MRI) const;
114 bool selectInsertElt(MachineInstr &I, MachineRegisterInfo &MRI) const;
115 bool selectBuildVector(MachineInstr &I, MachineRegisterInfo &MRI) const;
116 bool selectMergeValues(MachineInstr &I, MachineRegisterInfo &MRI) cons
430 unsupportedBinOp(const MachineInstr &I, const AArch64RegisterBankInfo &RBI, const MachineRegisterInfo &MRI, const AArch64RegisterInfo &TRI) argument
583 isValidCopy(const MachineInstr &I, const RegisterBank &DstBank, const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
620 selectSubregisterCopy(MachineInstr &I, MachineRegisterInfo &MRI, const RegisterBankInfo &RBI, Register SrcReg, const TargetRegisterClass *From, const TargetRegisterClass *To, unsigned SubReg) argument
645 getRegClassesForCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
670 selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
859 selectSelectOpc(MachineInstr &I, MachineRegisterInfo &MRI, const RegisterBankInfo &RBI) argument
873 selectFCMPOpc(MachineInstr &I, MachineRegisterInfo &MRI) argument
1039 getVectorShiftImm(Register Reg, MachineRegisterInfo &MRI) argument
1065 getVectorSHLImm(LLT SrcTy, Register Reg, MachineRegisterInfo &MRI) argument
1215 MachineRegisterInfo &MRI = MF.getRegInfo(); local
1253 MachineRegisterInfo &MRI = MF.getRegInfo(); local
1377 MachineRegisterInfo &MRI = MF.getRegInfo(); local
1418 MachineRegisterInfo &MRI = MF.getRegInfo(); local
2903 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); local
3245 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); local
3269 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); local
3294 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); local
3323 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); local
3374 MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo(); local
3476 MachineRegisterInfo &MRI = *MIB.getMRI(); local
3576 MachineRegisterInfo &MRI = *MIRBuilder.getMRI(); local
3678 MachineRegisterInfo &MRI = *MIB.getMRI(); local
4140 auto &MRI = MF.getRegInfo(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyMemIntrinsicResults.cpp86 const MachineRegisterInfo &MRI,
99 for (auto I = MRI.use_nodbg_begin(FromReg), E = MRI.use_nodbg_end();
150 const MachineRegisterInfo &MRI,
171 if (MRI.getRegClass(FromReg) != MRI.getRegClass(ToReg))
174 return replaceDominatedUses(MBB, MI, FromReg, ToReg, MRI, MDT, LIS);
183 MachineRegisterInfo &MRI = MF.getRegInfo(); local
193 MRI.leaveSSA();
195 assert(MRI
84 replaceDominatedUses(MachineBasicBlock &MBB, MachineInstr &MI, unsigned FromReg, unsigned ToReg, const MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS) argument
149 optimizeCall(MachineBasicBlock &MBB, MachineInstr &MI, const MachineRegisterInfo &MRI, MachineDominatorTree &MDT, LiveIntervals &LIS, const WebAssemblyTargetLowering &TLI, const TargetLibraryInfo &LibInfo) argument
[all...]
H A DWebAssemblyPeephole.cpp62 MachineRegisterInfo &MRI) {
66 Register NewReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg));
77 MachineRegisterInfo &MRI,
97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
120 Register NewReg = MRI.createVirtualRegister(RegClass);
138 MachineRegisterInfo &MRI = MF.getRegInfo(); local
170 if (MRI.getRegClass(NewReg) != MRI.getRegClass(OldReg))
173 Changed |= maybeRewriteToDrop(OldReg, NewReg, MO, MFI, MRI);
60 maybeRewriteToDrop(unsigned OldReg, unsigned NewReg, MachineOperand &MO, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI) argument
74 maybeRewriteToFallthrough(MachineInstr &MI, MachineBasicBlock &MBB, const MachineFunction &MF, WebAssemblyFunctionInfo &MFI, MachineRegisterInfo &MRI, const WebAssemblyInstrInfo &TII) argument
[all...]
H A DWebAssemblyOptimizeLiveIntervals.cpp73 MachineRegisterInfo &MRI = MF.getRegInfo(); local
77 MRI.leaveSSA();
79 assert(MRI.tracksLiveness() && "OptimizeLiveIntervals expects liveness");
83 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I < E; ++I) {
85 if (MRI.reg_nodbg_empty(Reg))
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp76 bool selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI,
78 bool selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI,
80 bool selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI,
82 bool selectConstant(MachineInstr &I, MachineRegisterInfo &MRI,
84 bool selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI,
86 bool selectZext(MachineInstr &I, MachineRegisterInfo &MRI,
88 bool selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI,
90 bool selectCmp(MachineInstr &I, MachineRegisterInfo &MRI,
92 bool selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI,
94 bool selectUadde(MachineInstr &I, MachineRegisterInfo &MRI,
314 MachineRegisterInfo &MRI = MF.getRegInfo(); local
473 X86SelectAddress(const MachineInstr &I, const MachineRegisterInfo &MRI, X86AddressMode &AM) argument
499 selectLoadStoreOp(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
559 selectFrameIndexOrGep(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
587 selectGlobalValue(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
633 selectConstant(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
690 selectTurnIntoCOPY( MachineInstr &I, MachineRegisterInfo &MRI, const unsigned DstReg, const TargetRegisterClass *DstRC, const unsigned SrcReg, const TargetRegisterClass *SrcRC) const argument
705 selectTruncOrPtrToInt(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
771 selectZext(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
882 selectAnyext(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
937 selectCmp(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
988 selectFCmp(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1079 selectUadde(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1138 selectExtract(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1195 emitExtractSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1233 emitInsertSubreg(unsigned DstReg, unsigned SrcReg, MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1271 selectInsert(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1329 selectUnmergeValues( MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) argument
1354 selectMergeValues( MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) argument
1403 selectCondBranch(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1424 materializeFP(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1517 selectDivRem(MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
1718 selectIntrinsicWSideEffects( MachineInstr &I, MachineRegisterInfo &MRI, MachineFunction &MF) const argument
[all...]
H A DX86RegisterBankInfo.cpp112 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP,
121 OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP);
148 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
151 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
153 if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
154 (Ty != MRI.getType(MI.getOperand(2).getReg())))
164 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
189 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
207 getInstrPartialMappingIdxs(MI, MRI, /* isFP */ true, OpRegBankIdx);
215 const LLT Ty0 = MRI
111 getInstrPartialMappingIdxs( const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, SmallVectorImpl<PartialMappingIdx> &OpRegBankIdx) argument
283 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCTargetDesc.h40 const MCRegisterInfo &MRI,
44 const MCRegisterInfo &MRI,
48 const MCRegisterInfo &MRI,
69 void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineLoopUtils.h37 MachineRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DMIRVRegNamerUtils.h45 MachineRegisterInfo &MRI; member in class:llvm::VRegRenamer
81 VRegRenamer(MachineRegisterInfo &MRI) : MRI(MRI) {} argument
H A DRegAllocBase.cpp61 MRI = &vrm.getRegInfo();
65 MRI->freezeReservedRegs(vrm.getMachineFunction());
75 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
77 if (MRI->reg_nodbg_empty(Reg))
93 if (MRI->reg_nodbg_empty(VirtReg->reg)) {
107 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
120 I = MRI->reg_instr_begin(VirtReg->reg), E = MRI->reg_instr_end();
137 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
149 if (MRI
[all...]
H A DOptimizePHIs.cpp38 MachineRegisterInfo *MRI; member in class:__anon1779::OptimizePHIs
78 MRI = &Fn.getRegInfo();
116 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
123 SrcMI = MRI->getVRegDef(SrcReg);
157 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DstReg)) {
181 if (!MRI->constrainRegClass(SingleValReg, MRI->getRegClass(OldReg)))
184 MRI->replaceRegWith(OldReg, SingleValReg);
188 MRI->clearKillFlags(SingleValReg);
H A DPHIEliminationUtils.cpp35 MachineRegisterInfo& MRI = MBB->getParent()->getRegInfo(); local
36 for (MachineInstr &RI : MRI.reg_instructions(SrcReg)) {
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DLegalizationArtifactCombiner.h28 MachineRegisterInfo &MRI; member in class:llvm::LegalizationArtifactCombiner
44 LegalizationArtifactCombiner(MachineIRBuilder &B, MachineRegisterInfo &MRI, argument
46 : Builder(B), MRI(MRI), LI(LI) {}
59 if (mi_match(SrcReg, MRI, m_GTrunc(m_Reg(TruncSrc)))) {
63 markInstAndDefDead(MI, *MRI.getVRegDef(SrcReg), DeadInsts);
70 if (mi_match(SrcReg, MRI,
82 auto *SrcMI = MRI.getVRegDef(SrcReg);
84 const LLT &DstTy = MRI.getType(DstReg);
108 if (mi_match(SrcReg, MRI, m_GTrun
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp48 MachineRegisterInfo &MRI) const;
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
66 bool validOpRegPair(MachineRegisterInfo &MRI, unsigned LHS, unsigned RHS,
70 bool validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize,
188 MachineRegisterInfo &MRI,
191 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI);
194 const unsigned Size = MRI.getType(Reg).getSizeInBits();
214 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
220 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TR
187 guessRegClass(unsigned Reg, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
213 selectCopy(MachineInstr &I, const TargetInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
233 selectMergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
264 selectUnmergeValues(MachineInstrBuilder &MIB, const ARMBaseInstrInfo &TII, MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI, const RegisterBankInfo &RBI) argument
503 validOpRegPair(MachineRegisterInfo &MRI, unsigned LHSReg, unsigned RHSReg, unsigned ExpectedSize, unsigned ExpectedRegBankID) const argument
512 validReg(MachineRegisterInfo &MRI, unsigned Reg, unsigned ExpectedSize, unsigned ExpectedRegBankID) const argument
846 auto &MRI = MF.getRegInfo(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsRegisterBankInfo.cpp173 Register Reg, const MachineRegisterInfo &MRI) {
174 assert(!MRI.getType(Reg).isPointer() &&
176 for (MachineInstr &UseMI : MRI.use_instructions(Reg)) {
181 addDefUses(NonCopyInstr->getOperand(0).getReg(), MRI);
188 Register Reg, const MachineRegisterInfo &MRI) {
189 assert(!MRI.getType(Reg).isPointer() &&
191 MachineInstr *DefMI = MRI.getVRegDef(Reg);
199 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
203 MRI.hasOneUse(Ret->getOperand(0).getReg())) {
204 Ret = &(*MRI
172 addDefUses( Register Reg, const MachineRegisterInfo &MRI) argument
187 addUseDef( Register Reg, const MachineRegisterInfo &MRI) argument
213 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
226 const MachineRegisterInfo &MRI = MI->getMF()->getRegInfo(); local
341 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
406 const MachineRegisterInfo &MRI = MF.getRegInfo(); local
669 MachineRegisterInfo &MRI = OpdMapper.getMRI(); local
[all...]
H A DMipsInstructionSelector.cpp43 bool isRegInGprb(Register Reg, MachineRegisterInfo &MRI) const;
44 bool isRegInFprb(Register Reg, MachineRegisterInfo &MRI) const;
47 bool selectCopy(MachineInstr &I, MachineRegisterInfo &MRI) const;
49 getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
51 MachineRegisterInfo &MRI) const;
90 MachineRegisterInfo &MRI) const {
91 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
95 MachineRegisterInfo &MRI) const {
96 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
100 MachineRegisterInfo &MRI) cons
255 MachineRegisterInfo &MRI = MF.getRegInfo(); local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/MCTargetDesc/
H A DSparcMCTargetDesc.cpp35 static MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, argument
39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
45 static MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, argument
49 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
90 const MCRegisterInfo &MRI) {
91 return new SparcInstPrinter(MAI, MII, MRI);
86 createSparcMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, const MCRegisterInfo &MRI) argument
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInstructionSelect.cpp86 MachineRegisterInfo &MRI = MF.getRegInfo(); local
129 if (isTriviallyDead(MI, MRI)) {
174 auto SrcRC = MRI.getRegClass(SrcReg);
175 auto DstRC = MRI.getRegClass(DstReg);
177 MRI.replaceRegWith(DstReg, SrcReg);
189 for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
193 if (!MRI.def_empty(VReg))
194 MI = &*MRI.def_instr_begin(VReg);
195 else if (!MRI.use_empty(VReg))
196 MI = &*MRI
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCTargetDesc.h34 const MCRegisterInfo &MRI,
39 const MCRegisterInfo &MRI,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMCTargetDesc.h36 const MCRegisterInfo &MRI,
40 const MCRegisterInfo &MRI,

Completed in 285 milliseconds

1234567891011>>