1//===-- AArch64MCTargetDesc.h - AArch64 Target Descriptions -----*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file provides AArch64 specific target descriptions.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
14#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64MCTARGETDESC_H
15
16#include "llvm/Support/DataTypes.h"
17
18#include <memory>
19
20namespace llvm {
21class formatted_raw_ostream;
22class MCAsmBackend;
23class MCCodeEmitter;
24class MCContext;
25class MCInstrInfo;
26class MCInstPrinter;
27class MCRegisterInfo;
28class MCObjectTargetWriter;
29class MCStreamer;
30class MCSubtargetInfo;
31class MCTargetOptions;
32class MCTargetStreamer;
33class StringRef;
34class Target;
35class Triple;
36class raw_ostream;
37class raw_pwrite_stream;
38
39MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
40                                          const MCRegisterInfo &MRI,
41                                          MCContext &Ctx);
42MCAsmBackend *createAArch64leAsmBackend(const Target &T,
43                                        const MCSubtargetInfo &STI,
44                                        const MCRegisterInfo &MRI,
45                                        const MCTargetOptions &Options);
46MCAsmBackend *createAArch64beAsmBackend(const Target &T,
47                                        const MCSubtargetInfo &STI,
48                                        const MCRegisterInfo &MRI,
49                                        const MCTargetOptions &Options);
50
51std::unique_ptr<MCObjectTargetWriter>
52createAArch64ELFObjectWriter(uint8_t OSABI, bool IsILP32);
53
54std::unique_ptr<MCObjectTargetWriter>
55createAArch64MachObjectWriter(uint32_t CPUType, uint32_t CPUSubtype,
56                              bool IsILP32);
57
58std::unique_ptr<MCObjectTargetWriter> createAArch64WinCOFFObjectWriter();
59
60MCTargetStreamer *createAArch64AsmTargetStreamer(MCStreamer &S,
61                                                 formatted_raw_ostream &OS,
62                                                 MCInstPrinter *InstPrint,
63                                                 bool isVerboseAsm);
64
65MCTargetStreamer *createAArch64ObjectTargetStreamer(MCStreamer &S,
66                                                    const MCSubtargetInfo &STI);
67
68namespace AArch64_MC {
69void initLLVMToCVRegMapping(MCRegisterInfo *MRI);
70}
71
72} // End llvm namespace
73
74// Defines symbolic names for AArch64 registers.  This defines a mapping from
75// register name to register number.
76//
77#define GET_REGINFO_ENUM
78#include "AArch64GenRegisterInfo.inc"
79
80// Defines symbolic names for the AArch64 instructions.
81//
82#define GET_INSTRINFO_ENUM
83#define GET_INSTRINFO_MC_HELPER_DECLS
84#include "AArch64GenInstrInfo.inc"
85
86#define GET_SUBTARGETINFO_ENUM
87#include "AArch64GenSubtargetInfo.inc"
88
89#endif
90