Searched refs:Def (Results 51 - 75 of 171) sorted by relevance

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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DGCNDPPCombine.cpp138 auto *Def = getVRegSubRegDef(getRegSubRegPair(OldOpnd), *MRI); local
139 if (!Def)
142 switch(Def->getOpcode()) {
148 auto &Op1 = Def->getOperand(1);
183 auto *Def = getVRegSubRegDef(CombOldVGPR, *MRI); local
184 DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
H A DGCNHazardRecognizer.h82 int checkVALUHazardsHelper(const MachineOperand &Def, const MachineRegisterInfo &MRI);
H A DSIFixSGPRCopies.cpp722 const MachineOperand &Def = DefMI->getOperand(0);
723 if (Def.isReg() &&
724 MO->getReg() == Def.getReg() &&
725 MO->getSubReg() == Def.getSubReg()) {
813 MachineInstr *Def = MRI->getVRegDef(InputReg);
815 if (Def->isCopy()) {
816 unsigned SrcReg = Def->getOperand(1).getReg();
825 else if (Def->isCopy() &&
826 TRI->isVectorRegister(*MRI, Def->getOperand(1).getReg())) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DRewriteStatepointsForGC.cpp395 /// instruction 'Def' is an input to 'Def' whose base is also a base of 'Def'.
398 /// defining value. The 'base defining value' for 'Def' is the transitive
521 Value *Def = CI->stripPointerCasts(); local
524 assert(cast<PointerType>(Def->getType())->getAddressSpace() ==
530 assert(!isa<CastInst>(Def) && "shouldn't find another cast here");
531 return findBaseDefiningValue(Def);
626 Value *Def = findBaseDefiningValueCached(I, Cache); local
627 auto Found = Cache.find(Def);
763 Value *Def = findBaseOrBDV(I, Cache); local
1769 Value *Def = Pair.first; local
1801 Value *Def = Pair.first; local
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H A DGVNHoist.cpp384 // Return true when there are memory uses of Def in BB.
385 bool hasMemoryUse(const Instruction *NewPt, MemoryDef *Def, argument
391 Instruction *OldPt = Def->getMemoryInst();
400 // Do not check whether MU aliases Def when MU occurs after OldPt.
404 // Do not check whether MU aliases Def when MU occurs before NewPt.
412 if (MemorySSAUtil::defClobbersUseOrDef(Def, MU, *AA))
438 // Return true when there are exception handling or loads of memory Def
439 // between Def and NewPt. This function is only called for stores: Def is
445 bool hasEHOrLoadsOnPath(const Instruction *NewPt, MemoryDef *Def, argument
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlan.h266 Value *get(VPValue *Def, unsigned Part) {
267 // If Values have been set for this Def return the one relevant for \p Part.
268 if (Data.PerPartOutput.count(Def))
269 return Data.PerPartOutput[Def][Part];
270 // Def is managed by ILV: bring the Values from ValueMap.
271 return Callback.getOrCreateVectorValues(VPValue2Value[Def], Part);
277 Value *get(VPValue *Def, const VPIteration &Instance) {
278 return Callback.getOrCreateScalarValue(VPValue2Value[Def], Instance);
282 void set(VPValue *Def, Value *V, unsigned Part) {
283 if (!Data.PerPartOutput.count(Def)) {
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/freebsd-11-stable/tools/tools/shlib-compat/
H A Dshlib-compat.py245 class Def(object): class in inherits:object
299 if isinstance(v, Def):
317 class AnonymousDef(Def):
319 Def.__init__(self, id, None, **kwargs)
345 class BaseTypeDef(Def):
364 class TypeAliasDef(Def):
374 class EnumerationTypeDef(Def):
407 class FunctionDef(Def):
416 class FunctionTypeDef(Def):
425 class ParameterDef(Def)
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/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/MCA/
H A DInstruction.h425 [](const WriteState &Def) { return Def.getNumUsers() > 0; });
430 for (const WriteState &Def : Defs)
431 NumUsers += Def.getNumUsers();
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CollectLOH.cpp173 /// Answer the following question: Can Def be one of the definition
532 const MachineOperand &Def = MI.getOperand(0); local
534 assert(Def.isReg() && Def.isDef() && "Expected reg def");
536 int DefIdx = mapRegToGPRIndex(Def.getReg());
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h107 virtual void computeOperandLatency(SDNode *Def, SDNode *Use,
H A DScheduleDAGSDNodes.cpp110 static void CheckForPhysRegDependency(SDNode *Def, SDNode *User, unsigned Op, argument
122 if (Def->getOpcode() == ISD::CopyFromReg &&
123 cast<RegisterSDNode>(Def->getOperand(1))->getReg() == Reg) {
125 } else if (Def->isMachineOpcode()) {
126 const MCInstrDesc &II = TII->get(Def->getMachineOpcode());
134 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
642 void ScheduleDAGSDNodes::computeOperandLatency(SDNode *Def, SDNode *Use,
655 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCBranchCoalescing.cpp429 for (auto &Def : MI.defs()) { // Looking at Def
430 for (auto &Use : MRI->use_instructions(Def.getReg())) {
540 for (auto &Def : I->defs())
541 for (auto &Use : MRI->use_instructions(Def.getReg())) {
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LoadValueInjectionLoadHardening.cpp364 [&](NodeAddr<DefNode *> Def) {
365 if (Transmitters.find(Def.Id) != Transmitters.end())
366 return; // Already analyzed `Def`
368 // Use RDF to find all the uses of `Def`
370 RegisterRef DefReg = DFG.getPRI().normalize(Def.Addr->getRegRef(DFG));
371 for (auto UseID : L.getAllReachedUses(DefReg, Def)) {
386 // For each use of `Def`, we want to know whether:
387 // (1) The use can leak the Def'ed value,
388 // (2) The use can further propagate the Def'ed value to more defs
391 continue; // Already visited this use of `Def`
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp618 void expand(SetTheory &ST, Record *Def, SetTheory::RecSet &Elts) override {
619 std::vector<Record*> Indices = Def->getValueAsListOfDefs("SubRegIndices");
621 ListInit *SubRegs = Def->getValueAsListInit("SubRegs");
623 PrintFatalError(Def->getLoc(), "SubRegIndices and SubRegs size mismatch");
625 PrintFatalError(Def->getLoc(),
632 ST.evaluate(SubRegs->getElement(i), Lists[i], Def->getLoc());
640 Record *RegisterCl = Def->getRecords().getClass("Register");
643 Def->getValueAsListOfStrings("RegAsmNames");
663 PrintFatalError(Def->getLoc(),
673 std::make_unique<Record>(Name, Def
1217 getSubRegIdx(Record *Def) argument
1226 getReg(Record *Def) argument
1262 getRegClass(Record *Def) argument
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H A DInstrDocsEmitter.cpp196 for (Record *Def : II->ImplicitDefs) {
199 OS << "``" << Def->getName() << "``";
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterPressure.cpp772 for (const RegisterMaskPair &Def : RegOpers.Defs) {
773 unsigned Reg = Def.RegUnit;
775 LaneBitmask PreviousMask = LiveRegs.erase(Def);
776 LaneBitmask NewMask = PreviousMask & ~Def.LaneMask;
778 LaneBitmask LiveOut = Def.LaneMask & ~PreviousMask;
842 for (const RegisterMaskPair &Def : RegOpers.Defs) {
843 unsigned RegUnit = Def.RegUnit;
845 (LiveRegs.contains(RegUnit) & Def.LaneMask).none())
933 for (const RegisterMaskPair &Def : RegOpers.Defs) {
934 LaneBitmask PreviousMask = LiveRegs.insert(Def);
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H A DRegisterCoalescer.cpp2451 SlotIndex Def = VNI->def; local
2452 MachineInstr *MI = Indexes->getInstructionFromIndex(Def);
2464 LiveQueryResult LRQ = LI.Query(Def);
2475 LiveQueryResult LRQ = S.Query(Def);
2965 SlotIndex Def = LR.getValNumInfo(i)->def; local
2971 LIS->pruneValue(Other.LR, Def, &EndPoints);
2979 if (!Def.isBlock()) {
2985 Indexes->getInstructionFromIndex(Def)->operands()) {
2994 // the live range also reaches the instruction at Def.
2996 EndPoints.push_back(Def);
3072 SlotIndex Def = LR.getValNumInfo(i)->def; local
3120 isDefInSubRange(LiveInterval &LI, SlotIndex Def) argument
3161 SlotIndex Def = VNI->def; local
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSSAUpdaterBulk.cpp141 for (auto &Def : R.Defines)
142 DefBlocks.insert(Def.first);
/freebsd-11-stable/contrib/llvm-project/clang/lib/Analysis/
H A DCallGraph.cpp98 if (FunctionDecl *Def = Ctor->getDefinition())
99 addCalledDecl(Def);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp103 bool Localizer::isLocalUse(MachineOperand &MOUse, const MachineInstr &Def, argument
109 return InsertMBB == Def.getParent();
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFGraph.h78 // - Def node contains: reaching def, sibling, first reached def, and first
86 // |Def |Use | |
88 // | V |Def |Def
164 // - Def.
275 Def = 0x0001 << 2, // 001 member in struct:llvm::rdf::NodeAttrs
287 Preserving = 0x0008 << 5, // 0001000, Def can keep original bits.
491 Def_struct Def; member in union:NodeBase::Ref_struct::__anon68
549 return getKind() == NodeAttrs::Def;
560 return Ref.Def
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DRDFDeadCode.cpp211 if (KindA == NodeAttrs::Use && KindB == NodeAttrs::Def)
213 if (KindA == NodeAttrs::Def && KindB == NodeAttrs::Use)
H A DHexagonHardwareLoops.cpp1377 MachineInstr *Def = MRI->getVRegDef(MO->getReg()); local
1378 LoopFeederPhi.insert(std::make_pair(MO->getReg(), Def));
1438 MachineInstr *Def = MRI->getVRegDef(Reg);
1439 if (!Def)
1444 if (Def->isPHI() && !phiMayWrapOrUnderflow(Def, EndVal, Def->getParent(),
1447 if (Def->isCopy() && !loopCountMayWrapOrUnderFlow(&(Def->getOperand(1)),
1448 EndVal, Def
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/freebsd-11-stable/contrib/llvm-project/clang/include/clang/Lex/
H A DPreprocessingRecord.h189 if (MacroDefinitionRecord *Def = getDefinition())
190 return Def->getName();
396 void RegisterMacroDefinition(MacroInfo *Macro, MacroDefinitionRecord *Def);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp174 MachineInstr *Def = MRI.getVRegDef(Reg); local
177 for (MachineOperand &DefMO : Def->explicit_uses()) {
184 return Def;

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