Searched refs:DAG (Results 26 - 50 of 146) sorted by relevance

123456

/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.h36 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
39 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
40 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
44 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
45 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
52 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) cons
282 CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
289 CreateLiveInRegisterRaw(SelectionDAG &DAG, const TargetRegisterClass *RC, unsigned Reg, EVT VT) const argument
[all...]
H A DR600ISelLowering.cpp1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
10 /// Custom DAG lowering for R600
472 // Custom DAG Lowering Operations
475 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
476 MachineFunction &MF = DAG.getMachineFunction();
479 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
480 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
481 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
482 case ISD::SHL_PARTS: return LowerSHLParts(Op, DAG);
484 case ISD::SRL_PARTS: return LowerSRXParts(Op, DAG);
694 vectorToVerticalVector(SelectionDAG &DAG, SDValue Vector) const argument
865 LowerUADDSUBO(SDValue Op, SelectionDAG &DAG, unsigned mainop, unsigned ovf) const argument
903 LowerImplicitParameter(SelectionDAG &DAG, EVT VT, const SDLoc &DL, unsigned DwordOffset) const argument
1578 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1683 CompactSwizzlableVector( SelectionDAG &DAG, SDValue VectorEntry, DenseMap<unsigned, unsigned> &RemapSwizzle) argument
1728 ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, DenseMap<unsigned, unsigned> &RemapSwizzle) argument
1768 OptimizeSwizzle(SDValue BuildVector, SDValue Swz[4], SelectionDAG &DAG, const SDLoc &DL) const argument
1844 SelectionDAG &DAG = DCI.DAG; local
[all...]
H A DSIISelLowering.cpp1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
10 /// Custom DAG lowering for SI
780 bool SITargetLowering::isFPExtFoldable(const SelectionDAG &DAG, unsigned Opcode, argument
786 !hasFP32Denormals(DAG.getMachineFunction());
1235 const SelectionDAG &DAG) const {
1409 SDValue SITargetLowering::lowerKernArgParameterPtr(SelectionDAG &DAG, argument
1413 const DataLayout &DL = DAG.getDataLayout();
1414 MachineFunction &MF = DAG.getMachineFunction();
1423 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
1425 SDValue BasePtr = DAG
1431 getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const argument
1438 convertArgType(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val, bool Signed, const ISD::InputArg *Arg) const argument
1469 lowerKernargMemParameter( SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Chain, uint64_t Offset, unsigned Align, bool Signed, const ISD::InputArg *Arg) const argument
1513 lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA, const SDLoc &SL, SDValue Chain, const ISD::InputArg &Arg) const argument
1562 getPreloadedValue(SelectionDAG &DAG, const SIMachineFunctionInfo &MFI, EVT VT, AMDGPUFunctionArgInfo::PreloadedValue PVID) const argument
2027 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
2378 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, bool IsThisReturn, SDValue ThisVal) const argument
2451 SelectionDAG &DAG = CLI.DAG; local
2678 SelectionDAG &DAG = CLI.DAG; local
3949 isFMADLegalForFAddFSub(const SelectionDAG &DAG, const SDNode *N) const argument
4108 adjustLoadValueTypeImpl(SDValue Result, EVT LoadVT, const SDLoc &DL, SelectionDAG &DAG, bool Unpacked) argument
4135 adjustLoadValueType(unsigned Opcode, MemSDNode *M, SelectionDAG &DAG, ArrayRef<SDValue> Ops, bool IsIntrinsic) const argument
4168 lowerIntrinsicLoad(MemSDNode *M, bool IsFormat, SelectionDAG &DAG, ArrayRef<SDValue> Ops) const argument
4203 lowerICMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG) argument
4239 lowerFCMPIntrinsic(const SITargetLowering &TLI, SDNode *N, SelectionDAG &DAG) argument
4580 getFPExtOrFPTrunc(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, EVT VT) const argument
5038 buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV, const SDLoc &DL, unsigned Offset, EVT PtrVT, unsigned GAFlags = SIInstrInfo::MO_NONE) argument
5126 copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL, SDValue V) const argument
5142 lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op, MVT VT, unsigned Offset) const argument
5154 emitNonHSAIntrinsicError(SelectionDAG &DAG, const SDLoc &DL, EVT VT) argument
5163 emitRemovedIntrinsicError(SelectionDAG &DAG, const SDLoc &DL, EVT VT) argument
5172 getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL, ArrayRef<SDValue> Elts) argument
5211 parseCachePolicy(SDValue CachePolicy, SelectionDAG &DAG, SDValue *GLC, SDValue *SLC, SDValue *DLC) argument
5236 constructRetValue(SelectionDAG &DAG, MachineSDNode *Result, ArrayRef<EVT> ResultTypes, bool IsTexFail, bool Unpacked, bool IsD16, int DMaskPop, int NumVDataDwords, const SDLoc &DL, LLVMContext &Context) argument
5316 parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE, SDValue *LWE, bool &IsTexFail) argument
7185 setBufferOffsets(SDValue CombinedOffset, SelectionDAG &DAG, SDValue *Offsets, unsigned Align) const argument
7219 handleByteShortBufferLoads(SelectionDAG &DAG, EVT LoadVT, SDLoc DL, ArrayRef<SDValue> Ops, MemSDNode *M) const argument
7238 handleByteShortBufferStores(SelectionDAG &DAG, EVT VDataType, SDLoc DL, SDValue Ops[], MemSDNode *M) const argument
7254 getLoadExtOrTrunc(SelectionDAG &DAG, ISD::LoadExtType ExtType, SDValue Op, const SDLoc &SL, EVT VT) argument
7275 SelectionDAG &DAG = DCI.DAG; local
7595 getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue GlueChain) argument
7615 getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL, EVT VT, SDValue A, SDValue B, SDValue C, SDValue GlueChain) argument
7692 getSPDenormModeValue(int SPDenormMode, SelectionDAG &DAG, const SDLoc &SL, const GCNSubtarget *ST) argument
8123 SelectionDAG &DAG = DCI.DAG; local
8213 getPermuteMask(SelectionDAG &DAG, SDValue V) argument
8444 SelectionDAG &DAG = DCI.DAG; local
8709 SelectionDAG &DAG = DCI.DAG; local
8741 isCanonicalized(SelectionDAG &DAG, SDValue Op, unsigned MaxDepth) const argument
8900 getCanonicalConstantFP( SelectionDAG &DAG, const SDLoc &SL, EVT VT, const APFloat &C) const argument
8933 SelectionDAG &DAG = DCI.DAG; local
9039 performIntMed3ImmCombine( SelectionDAG &DAG, const SDLoc &SL, SDValue Op0, SDValue Op1, bool Signed) const argument
9089 performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL, SDValue Op0, SDValue Op1) const argument
9145 SelectionDAG &DAG = DCI.DAG; local
9231 SelectionDAG &DAG = DCI.DAG; local
9281 SelectionDAG &DAG = DCI.DAG; local
9434 getFusedOpcode(const SelectionDAG &DAG, const SDNode *N0, const SDNode *N1) const argument
9498 getMad64_32(SelectionDAG &DAG, const SDLoc &SL, EVT VT, SDValue N0, SDValue N1, SDValue N2, bool Signed) argument
9510 SelectionDAG &DAG = DCI.DAG; local
9589 SelectionDAG &DAG = DCI.DAG; local
9746 SelectionDAG &DAG = DCI.DAG; local
9821 SelectionDAG &DAG = DCI.DAG; local
9917 SelectionDAG &DAG = DCI.DAG; local
10088 SelectionDAG &DAG = DCI.DAG; local
10514 buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL, uint64_t Val) argument
10520 wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr) const argument
10555 buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr, uint32_t RsrcDword1, uint64_t RsrcDword2And3) const argument
10777 computeKnownBitsForFrameIndex(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
10930 denormalsEnabledForType(const SelectionDAG &DAG, EVT VT) const argument
10943 isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN, unsigned Depth) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGAddressAnalysis.h1 //===- SelectionDAGAddressAnalysis.h - DAG Address Analysis -----*- C++ -*-===//
57 bool equalBaseIndex(const BaseIndexOffset &Other, const SelectionDAG &DAG,
61 const SelectionDAG &DAG) const {
63 return equalBaseIndex(Other, DAG, Off);
68 bool contains(const SelectionDAG &DAG, int64_t BitSize,
72 bool contains(const SelectionDAG &DAG, int64_t BitSize, argument
75 return contains(DAG, BitSize, Other, OtherBitSize, BitOffset);
84 const SelectionDAG &DAG, bool &IsAlias);
87 static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp51 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, argument
53 const Function &F = DAG.getMachineFunction().getFunction();
126 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, argument
132 InChain = DAG.getEntryNode();
141 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext());
155 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
156 getPointerTy(DAG.getDataLayout()));
158 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
159 TargetLowering::CallLoweringInfo CLI(DAG);
283 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EV argument
293 softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl, const SDValue OldLHS, const SDValue OldRHS, SDValue &Chain, bool IsSignaling) const argument
544 SelectionDAG &DAG = TLO.DAG; local
582 SelectionDAG &DAG = DCI.DAG; local
610 SimplifyMultipleUseDemandedBits( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const argument
2087 SelectionDAG &DAG = DCI.DAG; local
2103 getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG, const APInt &UndefOp0, const APInt &UndefOp1) argument
2643 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
2664 computeKnownBitsForFrameIndex(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
2717 SimplifyMultipleUseDemandedBitsForTargetNode( SDValue Op, const APInt &DemandedBits, const APInt &DemandedElts, SelectionDAG &DAG, unsigned Depth) const argument
2751 isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN, unsigned Depth) const argument
2870 SelectionDAG &DAG = DCI.DAG; local
2984 SelectionDAG &DAG = DCI.DAG; local
3015 SelectionDAG &DAG = DCI.DAG; local
3087 SelectionDAG &DAG = DCI.DAG; local
3122 SelectionDAG &DAG = DCI.DAG; local
4540 ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, const TargetLowering &TLI, SDValue Op, SelectionDAG *DAG) argument
4635 BuildExactSDIV(const TargetLowering &TLI, SDNode *N, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) argument
4694 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument
4708 BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl<SDNode *> &Created) const argument
4817 BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization, SmallVectorImpl<SDNode *> &Created) const argument
5008 SelectionDAG &DAG = DCI.DAG; local
5248 SelectionDAG &DAG = DCI.DAG; local
5482 isNegatibleForFree(SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, unsigned Depth) const argument
[all...]
H A DLegalizeTypesGeneric.cpp42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
57 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
58 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
62 auto &DL = DAG.getDataLayout();
68 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
69 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
74 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout()))
76 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo);
77 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi);
82 Lo = DAG
[all...]
H A DSelectionDAGBuilder.cpp1 //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
152 // Limit the width of DAG chains. This is important in general to prevent
153 // DAG-based analysis from blowing up. For example, alias analysis and
156 // future analyses are likely to have the same behavior. Limiting DAG width is
194 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
204 static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, argument
210 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V,
214 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
228 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits);
231 EVT HalfVT = EVT::getIntegerVT(*DAG
361 getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, Optional<CallingConv::ID> CallConv) argument
502 getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, Optional<CallingConv::ID> CallConv = None, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) argument
634 widenVectorToPartType(SelectionDAG &DAG, SDValue Val, const SDLoc &DL, EVT PartVT) argument
662 getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, Optional<CallingConv::ID> CallConv) argument
803 getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, const SDLoc &dl, SDValue &Chain, SDValue *Flag, const Value *V) const argument
890 getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, SDValue *Flag, const Value *V, ISD::NodeType PreferredExtendType) const argument
946 AddInlineAsmOperands(unsigned Code, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector<SDValue> &Ops) const argument
2505 getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain) argument
4376 SelectionDAG& DAG = SDB->DAG; local
4939 GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl) argument
4952 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, const SDLoc &dl) argument
4965 getF32Constant(SelectionDAG &DAG, unsigned Flt, const SDLoc &dl) argument
4971 getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, SelectionDAG &DAG) argument
5063 expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) argument
5085 expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) argument
5184 expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) argument
5281 expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) argument
5371 expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) argument
5383 expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI) argument
5411 ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG) argument
5464 expandDivFix(unsigned Opcode, const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue Scale, SelectionDAG &DAG, const TargetLowering &TLI) argument
7868 patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &MatchingOpInfo, SelectionDAG &DAG) argument
7897 getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, SDISelAsmOperandInfo &OpInfo, SelectionDAG &DAG) argument
7943 GetRegistersForValue(SelectionDAG &DAG, const SDLoc &DL, SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &RefOpInfo) argument
8628 lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op) argument
9635 SelectionDAG &DAG = SDB->DAG; local
[all...]
H A DDAGCombiner.cpp1 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
9 // This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run
10 // both before and after the DAG is legalized.
89 cl::desc("Enable DAG combiner's use of IR alias analysis"));
93 cl::desc("Enable DAG combiner's use of TBAA"));
98 cl::desc("Only use DAG-combiner alias analysis in this"
111 cl::desc("DAG combiner may split indexing from loads"));
115 cl::desc("DAG combiner enable merging multiple stores "
130 SelectionDAG &DAG; member in class:__anon83::DAGCombiner
145 /// due to nodes being deleted from the underlying DAG
2009 foldAddSubBoolOfMaskedVal(SDNode *N, SelectionDAG &DAG) argument
2050 foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) argument
2418 foldAddSubMasked1(bool IsAdd, SDValue N0, SDValue N1, SelectionDAG &DAG, const SDLoc &DL) argument
2542 flipBoolean(SDValue V, const SDLoc &DL, SelectionDAG &DAG, const TargetLowering &TLI) argument
2567 extractBooleanFlip(SDValue V, SelectionDAG &DAG, const TargetLowering &TLI, bool Force) argument
2753 combineADDCARRYDiamond(DAGCombiner &Combiner, SelectionDAG &DAG, SDValue X, SDValue Carry0, SDValue Carry1, SDNode *N) argument
2844 combineCarryDiamond(DAGCombiner &Combiner, SelectionDAG &DAG, const TargetLowering &TLI, SDValue Carry0, SDValue Carry1, SDNode *N) argument
2949 tryFoldToZero(const SDLoc &DL, const TargetLowering &TLI, EVT VT, SelectionDAG &DAG, bool LegalOperations) argument
3696 simplifyDivRem(SDNode *N, SelectionDAG &DAG) argument
5102 combineShiftAnd1ToBitTest(SDNode *And, SelectionDAG &DAG) argument
5776 visitORCommutative( SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) argument
5968 stripConstantMask(SelectionDAG &DAG, SDValue Op, SDValue &Mask) argument
5978 matchRotateHalf(SelectionDAG &DAG, SDValue Op, SDValue &Shift, SDValue &Mask) argument
6012 extractShiftForRotate(SelectionDAG &DAG, SDValue OppShift, SDValue ExtractFrom, SDValue &Mask, const SDLoc &DL) argument
6127 matchRotateSub(SDValue Pos, SDValue Neg, unsigned EltSize, SelectionDAG &DAG) argument
7234 combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) argument
8307 isLegalToCombineMinNumMaxNum(SelectionDAG &DAG, SDValue LHS, SDValue RHS, const TargetLowering &TLI) argument
8319 combineMinNumMaxNum(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode CC, const TargetLowering &TLI, SelectionDAG &DAG) argument
8368 foldSelectOfConstantsUsingSra(SDNode *N, SelectionDAG &DAG) argument
8700 ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) argument
9082 tryToFoldExtendOfConstant(SDNode *N, const TargetLowering &TLI, SelectionDAG &DAG, bool LegalTypes) argument
9474 tryToFoldExtOfExtload(SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType) argument
9505 tryToFoldExtOfLoad(SelectionDAG &DAG, DAGCombiner &Combiner, const TargetLowering &TLI, EVT VT, bool LegalOperations, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) argument
9545 tryToFoldExtOfMaskedLoad(SelectionDAG &DAG, const TargetLowering &TLI, EVT VT, SDNode *N, SDValue N0, ISD::LoadExtType ExtLoadType, ISD::NodeType ExtOpc) argument
9573 foldExtendedSignBitTest(SDNode *N, SelectionDAG &DAG, bool LegalOperations) argument
9846 isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, KnownBits &Known) argument
9878 widenCtPop(SDNode *Extend, SelectionDAG &DAG) argument
11087 getPPCf128HiElementSelector(const SelectionDAG &DAG) argument
11093 foldBitcastedFPLogic(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) argument
13010 foldFPToIntToFP(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) argument
13153 FoldIntToFPToInt(SDNode *N, SelectionDAG &DAG) argument
13446 visitFMinMax(SelectionDAG &DAG, SDNode *N, APFloat (*Op)(const APFloat &, const APFloat &)) argument
13682 canFoldInAddressingMode(SDNode *N, SDNode *Use, SelectionDAG &DAG, const TargetLowering &TLI) argument
14523 SelectionDAG *DAG; member in struct:__anon85::LoadedSlice
15042 SelectionDAG &DAG = DC->getDAG(); local
17029 scalarizeExtractedBinop(SDNode *ExtElt, SelectionDAG &DAG, bool LegalOperations) argument
17550 reduceBuildVecToShuffleWithZero(SDNode *BV, SelectionDAG &DAG) argument
17973 combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) argument
18038 combineConcatVectorOfExtracts(SDNode *N, SelectionDAG &DAG) argument
18302 narrowInsertExtractVectorBinOp(SDNode *Extract, SelectionDAG &DAG) argument
18338 narrowExtractedVectorBinOp(SDNode *Extract, SelectionDAG &DAG) argument
18457 narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) argument
18672 foldShuffleOfConcatUndefs(ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) argument
18796 combineShuffleOfScalars(ShuffleVectorSDNode *SVN, SelectionDAG &DAG, const TargetLowering &TLI) argument
18934 combineTruncationShuffle(ShuffleVectorSDNode *SVN, SelectionDAG &DAG) argument
18995 combineShuffleOfSplatVal(ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) argument
19073 replaceShuffleOfInsert(ShuffleVectorSDNode *Shuf, SelectionDAG &DAG) argument
19863 scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG) argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
10 // selection DAG.
524 SelectionDAG &DAG);
529 SelectionDAG &DAG);
534 SelectionDAG &DAG);
539 unsigned ShuffleKind, SelectionDAG &DAG);
544 unsigned ShuffleKind, SelectionDAG &DAG);
549 unsigned ShuffleKind, SelectionDAG &DAG);
579 SelectionDAG &DAG);
600 SelectionDAG &DAG);
[all...]
H A DPPCISelLowering.cpp1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
132 static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
888 // the DAG combine, so those aren't necessary.
1529 SelectionDAG &DAG) {
1530 bool IsLE = DAG.getDataLayout().isLittleEndian();
1560 SelectionDAG &DAG) {
1561 bool IsLE = DAG.getDataLayout().isLittleEndian();
1597 SelectionDAG &DAG) {
1599 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1603 bool IsLE = DAG
1528 isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
1559 isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
1596 isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
1664 isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) argument
1689 isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned ShuffleKind, SelectionDAG &DAG) argument
1779 isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven, unsigned ShuffleKind, SelectionDAG &DAG) argument
1808 isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind, SelectionDAG &DAG) argument
2150 getSplatIdxForPPCMnemonics(SDNode *N, unsigned EltSize, SelectionDAG &DAG) argument
2164 get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) argument
2341 SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG, unsigned EncodingAlignment) const argument
2392 fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) argument
2428 SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG, unsigned EncodingAlignment) const argument
2722 LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC, SelectionDAG &DAG) argument
2746 setUsesTOCBasePtr(SelectionDAG &DAG) argument
2750 getTOCEntry(SelectionDAG &DAG, const SDLoc &dl, SDValue GA) const argument
3470 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3488 LowerFormalArguments_32SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
3745 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG, SDValue ArgVal, const SDLoc &dl) const argument
3759 LowerFormalArguments_64SVR4( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4171 LowerFormalArguments_Darwin( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
4533 CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall, unsigned ParamSize) argument
4816 isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) argument
4845 StoreTailCallArgumentsToStackSlot( SelectionDAG &DAG, SDValue Chain, const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs, SmallVectorImpl<SDValue> &MemOpChains, const SDLoc &dl) argument
4862 EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, SDValue Chain, SDValue OldRetAddr, SDValue OldFP, int SPDiff, const SDLoc &dl) argument
4898 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, SDValue Arg, int SPDiff, unsigned ArgOffset, SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) argument
4916 EmitTailCallLoadFPAndRetAddr( SelectionDAG &DAG, int SPDiff, SDValue Chain, SDValue &LROpOut, SDValue &FPOpOut, const SDLoc &dl) const argument
4943 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument
4954 LowerMemOpCallTo( SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, SDValue Arg, SDValue PtrOff, int SPDiff, unsigned ArgOffset, bool isPPC64, bool isTailCall, bool isVector, SmallVectorImpl<SDValue> &MemOpChains, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments, const SDLoc &dl) argument
4978 PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, const SDLoc &dl, int SPDiff, unsigned NumBytes, SDValue LROp, SDValue FPOp, SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) argument
5015 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
5079 isIndirectCall(const SDValue &Callee, SelectionDAG &DAG, const PPCSubtarget &Subtarget, bool isPatchPoint) argument
5147 transformCallee(const SDValue &Callee, SelectionDAG &DAG, const SDLoc &dl, const PPCSubtarget &Subtarget) argument
5259 prepareIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, const SDLoc &dl) argument
5270 prepareDescriptorIndirectCall(SelectionDAG &DAG, SDValue &Callee, SDValue &Glue, SDValue &Chain, SDValue CallSeqStart, ImmutableCallSite CS, const SDLoc &dl, bool hasNest, const PPCSubtarget &Subtarget) argument
5363 buildCallOperands(SmallVectorImpl<SDValue> &Ops, CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg, bool isPatchPoint, bool hasNest, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue &Callee, int SPDiff, const PPCSubtarget &Subtarget, bool isIndirect) argument
5442 FinishCall( CallingConv::ID CallConv, const SDLoc &dl, bool isTailCall, bool isVarArg, bool isPatchPoint, bool hasNest, SelectionDAG &DAG, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, SDValue Glue, SDValue Chain, SDValue CallSeqStart, SDValue &Callee, int SPDiff, unsigned NumBytes, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
5510 SelectionDAG &DAG = CLI.DAG; local
5583 LowerCall_32SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
5821 createMemcpyOutsideCallSeq( SDValue Arg, SDValue PtrOff, SDValue CallSeqStart, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) const argument
5836 LowerCall_64SVR4( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
6497 LowerCall_Darwin( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
6987 truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT, SelectionDAG &DAG, SDValue ArgValue, MVT LocVT, const SDLoc &dl) argument
7003 LowerFormalArguments_AIX( SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
7079 LowerCall_AIX( SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, bool isPatchPoint, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, ImmutableCallSite CS) const argument
7704 LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI, SelectionDAG &DAG, const SDLoc &dl) const argument
7770 LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
7802 LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
7867 canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI, SelectionDAG &DAG, ISD::LoadExtType ET) const argument
7964 LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
7993 widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl) argument
8013 LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG, const SDLoc &dl) const argument
8473 BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
8493 BuildIntrinsicOp(unsigned IID, SDValue Op, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8502 BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8512 BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, const SDLoc &dl, EVT DestVT = MVT::Other) argument
8522 BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, EVT VT, SelectionDAG &DAG, const SDLoc &dl) argument
8930 GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const SDLoc &dl) argument
11989 getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps, bool &UseOneConstNR, bool Reciprocal) const argument
12011 getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled, int &RefinementSteps) const argument
12053 getBaseWithConstantOffset(SDValue Loc, SDValue &Base, int64_t& Offset, SelectionDAG &DAG) argument
12065 isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) argument
12105 isConsecutiveLS(SDNode *N, LSBaseSDNode *Base, unsigned Bytes, int Dist, SelectionDAG &DAG) argument
12218 findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) argument
12285 generateEquivalentSub(SDNode *N, int Size, bool Complement, bool Swap, SDLoc &DL, SelectionDAG &DAG) argument
12321 SelectionDAG &DAG = DCI.DAG; local
12361 SelectionDAG &DAG = DCI.DAG; local
12642 SelectionDAG &DAG = DCI.DAG; local
12943 SelectionDAG &DAG = DCI.DAG; local
12975 SelectionDAG &DAG = DCI.DAG; local
13056 combineBVOfConsecutiveLoads(SDNode *N, SelectionDAG &DAG) argument
13146 addShuffleForVecExtend(SDNode *N, SelectionDAG &DAG, SDValue Input, uint64_t Elems, uint64_t CorrectElems) argument
13180 combineBVOfVecSExt(SDNode *N, SelectionDAG &DAG) argument
13279 SelectionDAG &DAG = DCI.DAG; local
13467 SelectionDAG &DAG = DCI.DAG; local
13535 SelectionDAG &DAG = DCI.DAG; local
13601 SelectionDAG &DAG = DCI.DAG; local
13675 SelectionDAG &DAG = DCI.DAG; local
13712 SelectionDAG &DAG = DCI.DAG; local
14440 BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG, SmallVectorImpl<SDNode *> &Created) const argument
14473 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
15462 stripModuloOnShift(const TargetLowering &TLI, SDNode *N, SelectionDAG &DAG) argument
15542 combineADDToADDZE(SDNode *N, SelectionDAG &DAG, const PPCSubtarget &Subtarget) argument
15685 SelectionDAG &DAG = DCI.DAG; local
15878 SelectionDAG &DAG = DCI.DAG; local
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===//
10 // selection DAG.
102 static void errorUnsupported(SelectionDAG &DAG, const SDLoc &dl, argument
104 MachineFunction &MF = DAG.getMachineFunction();
105 DAG.getContext()->diagnose(
1126 // so that DAG combine doesn't try to turn it into uint_to_fp.
2068 SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, argument
2070 EVT PtrTy = getPointerTy(DAG.getDataLayout());
2072 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val);
2400 SelectionDAG &DAG) cons
2581 lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc, const SDLoc &Dl, SelectionDAG &DAG) argument
2612 Passv64i1ArgInRegs( const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg, SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA, CCValAssign &NextVA, const X86Subtarget &Subtarget) argument
2904 getv64i1Argument(CCValAssign &VA, CCValAssign &NextVA, SDValue &Root, SelectionDAG &DAG, const SDLoc &Dl, const X86Subtarget &Subtarget, SDValue *InFlag = nullptr) argument
2955 lowerRegToMasks(const SDValue &ValArg, const EVT &ValVT, const EVT &ValLoc, const SDLoc &Dl, SelectionDAG &DAG) argument
2991 LowerCallResult( SDValue Chain, SDValue InFlag, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, uint32_t *RegMask) const argument
3131 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument
3188 LowerMemArgument(SDValue Chain, CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, const CCValAssign &VA, MachineFrameInfo &MFI, unsigned i) const argument
[all...]
H A DX86SelectionDAGInfo.h28 bool isBaseRegConflictPossible(SelectionDAG &DAG,
34 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl,
39 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp24 SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
27 DAG.getMachineFunction().getSubtarget<ARMSubtarget>();
76 Entry.Ty = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
91 Src = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
93 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
96 Entry.Ty = Type::getInt32Ty(*DAG.getContext());
113 TargetLowering::CallLoweringInfo CLI(DAG);
117 TLI->getLibcallCallingConv(LC), Type::getVoidTy(*DAG.getContext()),
118 DAG
23 EmitSpecializedLibcall( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, RTLIB::Libcall LC) const argument
127 EmitTargetCodeForMemcpy( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
241 EmitTargetCodeForMemmove( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument
249 EmitTargetCodeForMemset( SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, SDValue Size, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
10 // selection DAG.
321 SelectionDAG &DAG) const override;
324 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
330 SelectionDAG &DAG) const override;
333 // DAG node.
385 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
392 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, argument
395 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, T
411 getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned Flag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
424 getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, unsigned HiFlag, unsigned LoFlag, SDValue Chain, const MachinePointerInfo &PtrInfo) const argument
487 getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, bool IsN64) const argument
[all...]
H A DMipsSEISelLowering.cpp1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
409 SDValue MipsSETargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
411 return MipsTargetLowering::LowerOperation(Op, DAG);
419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0));
420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1),
450 SelectionDAG &DAG) const {
452 case ISD::LOAD: return lowerLOAD(Op, DAG);
453 case ISD::STORE: return lowerSTORE(Op, DAG);
454 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
455 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
482 performANDCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
597 performORCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
717 shouldTransformMulToShiftsAddsSubs(APInt C, EVT VT, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
793 genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, EVT ShiftTy, SelectionDAG &DAG) argument
829 performMULCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering::DAGCombinerInfo &DCI, const MipsSETargetLowering *TL, const MipsSubtarget &Subtarget) argument
845 performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
870 performSHLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
893 performSRACombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
939 performSRLCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) argument
968 performSETCCCombine(SDNode *N, SelectionDAG &DAG) argument
981 performVSELECTCombine(SDNode *N, SelectionDAG &DAG) argument
998 performXORCombine(SDNode *N, SelectionDAG &DAG, const MipsSubtarget &Subtarget) argument
1027 SelectionDAG &DAG = DCI.DAG; local
1058 N->printrWithDepth(dbgs(), &DAG); dbgs() << "\\n=> \\n"; local
1059 Val.getNode()->printrWithDepth(dbgs(), &DAG); dbgs() << "\\n"); local
1287 initAccumulator(SDValue In, const SDLoc &DL, SelectionDAG &DAG) argument
1295 extractLOHI(SDValue Op, const SDLoc &DL, SelectionDAG &DAG) argument
1313 lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1362 lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) argument
1375 lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) argument
1419 lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, bool IsSigned = false) argument
1428 getBuildVectorSplat(EVT VecTy, SDValue SplatValue, bool BigEndian, SelectionDAG &DAG) argument
1464 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument
1508 truncateVecElts(SDValue Op, SelectionDAG &DAG) argument
1521 lowerMSABitClear(SDValue Op, SelectionDAG &DAG) argument
1531 lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) argument
2294 lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument
2368 lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, const MipsSubtarget &Subtarget) argument
2554 lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2635 isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2667 lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2713 lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2760 lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2807 lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2855 lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2898 lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
2934 lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, SmallVector<int, 16> Indices, SelectionDAG &DAG) argument
[all...]
H A DMipsSEISelLowering.h1 //===- MipsSEISelLowering.h - MipsSE DAG Lowering Interface -----*- C++ -*-===//
48 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
74 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
75 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
76 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
79 SelectionDAG &DAG) const;
81 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
82 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
83 SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
84 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.h1 //===- ARCISelLowering.h - ARC DAG Lowering Interface -----------*- C++ -*-===//
10 // selection DAG.
66 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
68 /// This method returns the name of a target specific DAG node.
84 SDLoc dl, SelectionDAG &DAG,
87 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
88 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
89 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h1 //===-- SparcISelLowering.h - Sparc DAG Lowering Interface ------*- C++ -*-===//
10 // selection DAG.
57 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
67 const SelectionDAG &DAG,
83 SelectionDAG &DAG) const override;
129 const SDLoc &dl, SelectionDAG &DAG,
134 const SDLoc &dl, SelectionDAG &DAG,
139 const SDLoc &dl, SelectionDAG &DAG,
153 const SDLoc &dl, SelectionDAG &DAG) const override;
158 const SDLoc &DL, SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.h1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
10 // selection DAG.
452 SelectionDAG &DAG) const override;
498 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
500 SelectionDAG &DAG) const override;
502 SelectionDAG &DAG) const override;
509 const SDLoc &DL, SelectionDAG &DAG,
521 SelectionDAG &DAG) const override;
529 const SelectionDAG &DAG,
535 const SelectionDAG &DAG,
[all...]
H A DSystemZISelLowering.cpp1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
1185 SelectionDAG &DAG) const {
1192 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
1199 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
1206 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
1213 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
1220 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
1225 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
1271 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, argument
1277 Value = DAG
1300 convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL, CCValAssign &VA, SDValue Value) argument
1324 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1492 SelectionDAG &DAG = CLI.DAG; local
1929 emitIntrinsicWithCCAndChain(SelectionDAG &DAG, SDValue Op, unsigned Opcode) argument
1949 emitIntrinsicWithCC(SelectionDAG &DAG, SDValue Op, unsigned Opcode) argument
1992 adjustZeroCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2012 adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2176 adjustForSubtraction(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2246 adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2377 adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2468 adjustForRedundantAnd(SelectionDAG &DAG, const SDLoc &DL, Comparison &C) argument
2486 getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode, SDValue Call, unsigned CCValid, uint64_t CC, ISD::CondCode Cond) argument
3825 lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG, unsigned Opcode) const argument
4076 getCCResult(SelectionDAG &DAG, SDValue CCReg) argument
4397 getPermuteNode(SelectionDAG &DAG, const SDLoc &DL, const Permute &P, SDValue Op0, SDValue Op1) argument
4426 getGeneralPermuteNode(SelectionDAG &DAG, const SDLoc &DL, SDValue *Ops, const SmallVectorImpl<int> &Bytes) argument
4544 getNode(SelectionDAG &DAG, const SDLoc &DL) argument
4632 buildScalarToVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Value) argument
4648 buildMergeScalars(SelectionDAG &DAG, const SDLoc &DL, EVT VT, SDValue Op0, SDValue Op1) argument
4664 joinDwords(SelectionDAG &DAG, const SDLoc &DL, SDValue Op0, SDValue Op1) argument
4685 tryBuildVectorShuffle(SelectionDAG &DAG, BuildVectorSDNode *BVN) argument
4744 buildVector(SelectionDAG &DAG, const SDLoc &DL, EVT VT, SmallVectorImpl<SDValue> &Elems) const argument
5450 SelectionDAG &DAG = DCI.DAG; local
5589 SelectionDAG &DAG = DCI.DAG; local
5618 SelectionDAG &DAG = DCI.DAG; local
5639 SelectionDAG &DAG = DCI.DAG; local
5666 SelectionDAG &DAG = DCI.DAG; local
5700 SelectionDAG &DAG = DCI.DAG; local
5765 SelectionDAG &DAG = DCI.DAG; local
5826 SelectionDAG &DAG = DCI.DAG; local
5865 SelectionDAG &DAG = DCI.DAG; local
5906 SelectionDAG &DAG = DCI.DAG; local
5940 SelectionDAG &DAG = DCI.DAG; local
6006 SelectionDAG &DAG = DCI.DAG; local
6061 SelectionDAG &DAG = DCI.DAG; local
6266 SelectionDAG &DAG = DCI.DAG; local
6290 SelectionDAG &DAG = DCI.DAG; local
6355 SelectionDAG &DAG = DCI.DAG; local
6506 computeKnownBitsBinOp(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo) argument
6521 computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
6615 computeNumSignBitsBinOp(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth, unsigned OpNo) argument
6639 ComputeNumSignBitsForTargetNode( SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h1 //==-- AArch64ISelLowering.h - AArch64 DAG Lowering Interface ----*- C++ -*-==//
10 // selection DAG.
317 const SelectionDAG &DAG,
322 // *DAG* representation of pointers will always be 64-bits. They will be
323 // truncated and extended when transferred to memory, but the 64-bit DAG
345 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
375 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
521 const SelectionDAG &DAG) const override {
525 bool NoFloat = DAG.getMachineFunction().getFunction().hasFnAttribute(
560 SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h1 //===-- RISCVISelLowering.h - RISCV DAG Lowering Interface ------*- C++ -*-===//
10 // selection DAG.
81 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
83 SelectionDAG &DAG) const override;
89 const SelectionDAG &DAG,
92 // This method returns the name of a target specific DAG node.
105 SelectionDAG &DAG) const override;
130 bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override {
131 if (DAG.getMachineFunction().getFunction().hasMinSize())
168 const SDLoc &DL, SelectionDAG &DAG,
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
10 // into a selection DAG.
156 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG)
168 SelectionDAG &DAG, const SDLoc &dl) {
169 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
170 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
197 const SDLoc &dl, SelectionDAG &DAG) const {
202 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
203 *DAG.getContext());
218 Chain = DAG
166 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, const SDLoc &dl) argument
318 LowerCallResult( SDValue Chain, SDValue Glue, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals, const SmallVectorImpl<SDValue> &OutVals, SDValue Callee) const argument
374 SelectionDAG &DAG = CLI.DAG; local
745 LowerFormalArguments( SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
1128 GetDynamicTLSAddr(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, SDValue Glue, EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) const argument
2152 getBuildVectorConstInts(ArrayRef<SDValue> Values, MVT VecTy, SelectionDAG &DAG, MutableArrayRef<ConstantInt*> Consts) const argument
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h1 //===-- MSP430ISelLowering.h - MSP430 DAG Lowering Interface ----*- C++ -*-===//
10 // selection DAG.
83 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
86 /// DAG node.
89 SDValue LowerShifts(SDValue Op, SelectionDAG &DAG) const;
90 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
91 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
92 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
93 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
94 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) cons
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblySelectionDAGInfo.h25 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
31 SDValue EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl,
36 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &DL,

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