Searched refs:getReg (Results 201 - 225 of 244) sorted by relevance

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/freebsd-10.2-release/contrib/llvm/lib/Target/XCore/Disassembler/
H A DXCoreDisassembler.cpp82 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { function
217 unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
229 unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/
H A DIfConversion.cpp976 unsigned Reg = Ops->getReg();
984 unsigned Reg = Ops->getReg();
1004 if (DontKill.contains(O->getReg(), MCRI))
1380 unsigned Reg = MO.getReg();
1469 unsigned Reg = MO.getReg();
H A DMachineScheduler.cpp1185 unsigned SrcReg = Copy->getOperand(1).getReg();
1189 unsigned DstReg = Copy->getOperand(0).getReg();
1262 if (I->getKind() != SDep::Data || I->getReg() != LocalReg)
1278 if (I->getKind() != SDep::Anti || I->getReg() != GlobalReg)
2399 MI->getOperand(ScheduledOper).getReg()))
2405 MI->getOperand(UnscheduledOper).getReg()))
2797 if (I->getKind() != SDep::Data || !TRI->isPhysicalRegister(I->getReg()))
H A DSplitKit.cpp452 .addReg(Edit->getReg());
566 MI->readsVirtualRegister(Edit->getReg())) {
667 if (AtBegin || !MBBI->readsVirtualRegister(Edit->getReg())) {
971 /// rewriteAssigned - Rewrite all uses of Edit->getReg().
973 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(Edit->getReg()),
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfDebug.cpp1338 MI->getOperand(0).isReg() && MI->getOperand(0).getReg() &&
1340 (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == 0U));
1356 MLoc.set(MI->getOperand(0).getReg());
1358 MLoc.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
1432 && !Begin->getOperand(0).getReg())
1668 LiveUserVar[MI->getOperand(0).getReg()] = Var;
1728 if (!MOI->isReg() || !MOI->isDef() || !MOI->getReg())
1730 for (MCRegAliasIterator AI(MOI->getReg(), TRI, true); AI.isValid();
1753 Prev->getOperand(0).getReg() != Reg)
2743 MachineLocation TLoc(Loc.getReg(), D
[all...]
H A DAsmPrinter.cpp552 unsigned RegNo = MI->getOperand(0).getReg();
564 Str += AP.TM.getRegisterInfo()->getName(Op.getReg());
618 Reg = MI->getOperand(0).getReg();
837 int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
839 for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid() && Reg < 0;
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp443 unsigned dest = MI->getOperand(0).getReg();
444 unsigned ptr = MI->getOperand(1).getReg();
445 unsigned incr = MI->getOperand(2).getReg();
528 unsigned dest = MI->getOperand(0).getReg();
529 unsigned ptr = MI->getOperand(1).getReg();
530 unsigned incr = MI->getOperand(2).getReg();
611 unsigned dest = MI->getOperand(0).getReg();
612 unsigned ptr = MI->getOperand(1).getReg();
613 unsigned oldval = MI->getOperand(2).getReg();
614 unsigned newval = MI->getOperand(3).getReg();
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp190 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
204 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
215 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
261 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
276 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
720 cast<RegisterSDNode>(Node->getOperand(i))->getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp339 MCOp = MCOperand::CreateReg(encodeVirtualRegister(MO.getReg()));
559 unsigned RegNo = MI->getOperand(0).getReg();
2062 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
2063 if (MO.getReg() == NVPTX::VRDepot)
2066 O << NVPTXInstPrinter::getRegisterName(MO.getReg());
2068 emitVirtualRegister(MO.getReg(), O);
/freebsd-10.2-release/contrib/llvm/utils/TableGen/
H A DCodeGenRegisters.h558 CodeGenRegister *getReg(Record*);
H A DDAGISelMatcherGen.cpp29 const CodeGenRegister *Reg = T.getRegBank().getReg(R);
596 CGP.getTargetInfo().getRegBank().getReg(Def);
H A DCodeGenInstruction.cpp475 .contains(T.getRegBank().getReg(ADI->getDef())))
H A DCodeGenTarget.cpp231 const CodeGenRegister *Reg = getRegBank().getReg(R);
/freebsd-10.2-release/contrib/llvm/include/llvm/CodeGen/
H A DMachineOperand.h258 /// getReg - Returns the register number.
259 unsigned getReg() const { function in class:llvm::MachineOperand
H A DScheduleDAG.h220 /// getReg - Return the register associated with this edge. This is
223 unsigned getReg() const { function in class:llvm::SDep
225 "getReg called on non-register dependence edge!");
/freebsd-10.2-release/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1919 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
6214 unsigned dest = MI->getOperand(0).getReg();
6215 unsigned ptr = MI->getOperand(1).getReg();
6216 unsigned oldval = MI->getOperand(2).getReg();
6217 unsigned newval = MI->getOperand(3).getReg();
6312 unsigned dest = MI->getOperand(0).getReg();
6313 unsigned ptr = MI->getOperand(1).getReg();
6314 unsigned incr = MI->getOperand(2).getReg();
6407 unsigned dest = MI->getOperand(0).getReg();
6408 unsigned ptr = MI->getOperand(1).getReg();
[all...]
H A DARMBaseRegisterInfo.cpp750 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp109 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
134 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4,
150 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
1033 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
1279 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg)
2959 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
2960 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
2961 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
2981 unsigned DestReg = MI->getOperand(0).getReg();
2982 unsigned AddrReg = MI->getOperand(1).getReg();
[all...]
/freebsd-10.2-release/contrib/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp77 // because of the virtual getReg() method, which needs to distinguish
180 virtual unsigned getReg() const LLVM_OVERRIDE {
232 Inst.addOperand(MCOperand::CreateReg(getReg()));
/freebsd-10.2-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp425 OS << ' ' << PrintReg(R->getReg(), G ? G->getTarget().getRegisterInfo() :0);
/freebsd-10.2-release/contrib/llvm/lib/MC/
H A DMCModuleYAML.cpp224 Out << "R" << IRI->MRI.getName(Val.MCOp.getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp413 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp469 unsigned Reg = MO.getReg();
/freebsd-10.2-release/contrib/llvm/lib/Target/Mips/
H A DMipsLongBranch.cpp235 MIB.addReg(MO.getReg());
/freebsd-10.2-release/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86AsmBackend.cpp255 if (Op.isReg() && Op.getReg() == X86::RIP)

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